Circuit arrangement for frequency division by non-integral divisors

Claim 1

A circuit arrangement for generating an output frequency by division of pulses of an input frequency, comprising a first adjustable frequency divider providing the output of said circuit arrangement, a further adjustable frequency divider, a first gate having an output connected to the input of said first adjustable frequency divider and having a first input connected to the output of said further adjustable frequency divider, means applying the input frequency to a second input of said first gate, said further adjustable frequency divider suppressing selectable pulses of said input frequency applied to said first gate, the division ratio of at least one of said first and said further frequency dividers being adjustable in response to selection signals, two cascade connected counters providing said selection signals, a second gate having an output connected to an input of said cascade counters and having a first input connected to receive said input frequency, and timing means for providing an enabling signal to a second input of said second gate for a time interval equal to a predetermined number of periods of said input frequency, said cascaded counter counting the pulses of said input frequency during said predetermined time interval and adjusting the division ratio of said one of said adjustable frequency dividers in accordance with the number of pulses of said input frequency counted by said counter.