US4308470A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital-to-analog switching interface circuit
Assignee: National Semiconductor Corp
•
Filing: 1980-03-25
•
Granted: 1981-12-29
•
Expires: 2000-03-25
Abstract
Abstract A transistor interface circuit for switching analog differential pairs in response to a flip-flop or combinational logic, both output signals of which remain either high or low during switching transitions. This circuitry prevents the differential pair from momentarily saturating or shutting off during the switching transition.
Inventors
- 👤 Gerard S. Regnier
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 19:51
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/51; H03K17/56; H03K17/60; H03K17/603
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
179 words
A digital-to-analog switching interface circuit for producing transient-free output signals in response to a pair of binary input switching signals having the same output states during the switching transition, said interface circuit comprising: first and second PNP transistors having intercoupled emitters coupled to a positive current source, the collectors of said first and second transistors being respectively coupled to the anodes of first and second diodes, the cathodes of which are coupled together and through a third diode to negative reference; first and second signal output terminals coupled respectively to the collectors of said first and second PNP transistors; and third and fourth PNP transistors, the emitters of which are coupled respectively to the base elements of said first and second PNP transistors, the base of said third transistor being coupled to the collector of said fourth transistor, the base of said fourth transistor being coupled to the collector of said third transistor, the bases of said third and fourth transistors being coupled respectively through fourth and fifth diodes to first and second input terminals of said interface circuitry.
Claim 2
Dependent Claim
179 words
A digital-to-analog switching interface circuit for producing transient-free output signals in response to a pair of binary input switching signals having the same output states during the switching transition, said interface circuit comprising: first and second PNP transistors having intercoupled emitters coupled to a positive current source, the collectors of said first and second transistors being respectively coupled to the anodes of first and second diodes, the cathodes of which are coupled together and through a third diode to negative reference; first and second signal output terminals coupled respectively to the collectors of said first and second PNP transistors; and third and fourth PNP transistors, the emitters of which are coupled respectively to the base elements of said first and second PNP transistors, the base of said third transistor being coupled to the collector of said fourth transistor, the base of said fourth transistor being coupled to the collector of said third transistor, the bases of said third and fourth transistors being coupled respectively through fourth and fifth diodes to first and second input terminals of said interface circuitry.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-12-28 | 1985-06-29 | 1985-12-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-12-28 | 1989-06-29 | 1989-12-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-12-28 | 1993-06-29 | 1993-12-29 | $7700.00 | Window Closed / Lapsed |