Bipolar receiver

Claim 2

A communication circuit for converting bipolar input signals into monopolar signals suitable for fabrication by integrated circuit technology comprising: an input stage for receiving said bipolar signals, said input stage including two input transistors, a first inverter transistor, a first amplifier transistor and a switching transistor, each having a base electrode, a collector electrode and an emitter electrode, said two input transistors having base electrodes connected in parallel to receive said bipolar signals simultaneously and being responsive to said input signals of a first and an opposite polarity, respectively, two provide first and second control signals at their collector electrodes, said inverter transistor having a base electrode connected to receive said first control signal and being responsive to provide an inverted signal at a base electrode of said first amplifier transistor, said first amplifier transistor being responsive to provide a first current signal from a first voltage source and said switching transistor being responsive to said second control signal to provide a second current signal from a second voltage source; a biasingfilter connection means being connected to said input stage to receive said first and second current signals and being responsive to provide a voltage signal, said connection means having a capacitor connected thereto for establishing a rise and a fall slope of said voltage signal when said input signals change from said opposite to first and first to opposite polarity, respectively; a voltage clamping means connected to said input stage for receiving said voltage signal and being responsive during a succession of time intervals to provide a clamped signal having successively said rise slope, a first polarity clamped level, said fall slope, and an opposite polarity clamped level; and intermediate stage including first and second emitter-coupled transistors forming a differential amplifier, a second inverter transistor and a second amplifier transistor, said first emitter-coupled transistor being connected to said clamping means to receive said clamped signal at a base electrode of said first emitter-coupled transistor and being responsive at a first and an opposite polarity response level to bias said second emitter-coupled transistor in conductive and nonconductive conditions to provide first and second amplifier signals at a collector electrode of said second emItter-coupled transistor, said clamping means providing clamped levels having a greater level than said response levels to control a delay time between said clamped and response levels, said second inverter transistor having a base electrode connected to said collector electrode of said second emitter-coupled transistor to receive said first and second amplifier signals and being responsive to provide first and second inverted signals at a base electrode of said second amplifier transistor, said second amplifier transistor being responsive to said first and second inverted signals to provide first and second gating signals; and an output stage having an output transistor with a base electrode connected to said intermediate stage to receive said first and second gating signals and being responsive to provide first and second output signals of different voltage levels and like polarity at an output terminal.

Claim 3

The communication circuit of claim 1 further comprising: a dual thresholding means comprising a pair of diodes, one of said diodes being connected between an emitter electrode of each of said input transistors and a reference potential, said thresholding means operable to bias the first input transistor in a conducting condition when a bipolar signal of said first polarity signal exceeds a predetermined threshold voltage level and being operable to bias the second input transistor in a conducting condition when a bipolar signal of said opposite polarity signal exceeds a predetermined threshold voltage level.

Claim 4

The communication circuit of claim 1 further comprising an impedance means connected between said emitter electrode of said second amplifier transistor and a base electrode of said second emitter-coupled transistor to provide a positive feedback path, said path being from said emitter electrode of the second emitter-coupled transistor through said second inverter transistor, second amplifier transistor and said impedance means to the base electrode of said second emitter-coupled transistor and being operable in response to said first and second amplifier signals to provide snap action of said second emitter-follower transistor for providing an increase in transition speed between changes in output signal voltage levels.

Claim 5

A bipolar receiver circuit suitable for fabrication by integrated circuit techniques comprising: a first and a second input transistor each having a base electrode, a collector electrode, and an emitter electrode, said base electrode connected in parallel to a common input lead to receive a succession of input signals having alternate polarity input voltage levels, said first and second input transistors being NPN and PNP types, respectively; a pair of threshold diodes, one of said diodes being connected between the emitter electrode of each of said input transistors and ground potential, one of said diodes being operable to bias the first input transistor into a conductive condition during the presence of an input signal having a level exceeding a predetermined positive polarity threshold level at its base electrode and one of said diodes being operable to bias the second input transistor into a conductive condition to provide first and second control signals on their respective collector electrodes; a first doublet having a first PNP transistor with an emitter electrode connected to a collector electrode of a first NPN transistor having a base electrode connected to the collector electrode of said first input transistor and responsive to said first control signal to provide a first inverted signal to the base electrode of said first NPN transistor for biasing said first NPN transistor into a conductive condition for providing a first current signal from a first voltage source on an emitter electrode; an NPN-type switching transistor having a base electrode connected to the collector electrode of said second input transistor to receive said second control signal and being in a conductive condition during thE presence of said second control signal to provide a second current signal from a second voltage source on an emitter electrode; a biasing-filtering connection means having a resistor connected between a connection terminal and the emitter electrodes of said first NPN transistor and said switching transistor at a junction point to receive said first and second current signals and being responsive to provide a voltage signal, said connection means having a capacitor connected to said terminal for establishing a rise and a fall slope of said voltage signal when said input signals change from said opposite to first and first to opposite polarity, respectively; a pair of oppositely poled clamping diodes connected between said junction point and a reference potential for receiving said voltage signal and being responsive during a succession of time intervals to provide a clamped signal having successively said rise slope, a first polarity clamped level, said fall slope, and an opposite polarity clamped level; first and second emitter-coupled NPN transistors forming a differential amplifier and having a base electrode of said first emitter-coupled NPN transistor connected to said junction point to receive said clamped signal to receive said first emitter-coupled transistor being operable in response to a first and an opposite polarity response level at its base electrode to bias said second emitter-coupled transistor into a conductive and a nonconductive condition, respectively, to provide a first and a second amplifier signal at its collector electrode, said clamping diodes providing clamped levels having a greater level than said response levels to control a delay time between said clamped and response levels; a second doublet having a second PNP transistor with an emitter electrode connected to a collector electrode of a second NPN transistor, said second PNP transistor having a base electrode connected to the collector electrode of said second emitter-coupled transistor to receive said first and second amplifier signals and being responsive to provide a second inverted signal to the base electrode of said second NPN transistor to bias said second NPN transistor into conductive and nonconductive conditions, respectively, to provide a first and a second gating signal on its emitter electrode; and an output NPN transistor having a base electrode connected to the emitter electrode of said second NPN transistor to receive said first and second gating signals and being in a conductive and nonconductive state in response to the presence of said first and second gating signals, respectively, to provide first and second output signals at a collector electrode, said output signals having different first and second voltage levels of like polarity.

Claim 6

A bipolar receiver circuit suitable for fabrication by integrated circuit techniques comprising: a first and a second input transistor each having a base electrode, a collector electrode, and an emitter electrode, said base electrode connected in parallel to a common input lead to receive a succession of input signals having alternate polarity input voltage levels, said first and second input transistors being NPN and PNP types, respectively; a pair of threshold diodes, one of said diodes being connected between the emitter electrode of each of said input transistors and ground potential, one of said diodes being operable to bias the first input transistor into a conductive condition during the presence of an input signal having a level exceeding a predetermined positive polarity threshold level at its base electrode and one of said diodes being operable to bias the second input transistor into a conductive condition to provide first and second control signals on their respective collector electrodes; a first doublet having a first PNP transistor with an emitter electrode connected to a collector electrode of a first NPN transistor having a base electrode connected to the collector electrode of said first input transistor and responsive to said first control signal to provide a first inverted signal to the base electrode of said first NPN transistor for biasing said first NPN transistor into a conductive condition for providing a first current signal from a first voltage source on an emitter electrode; an NPN-type switching transistor having a base electrode connected to the collector electrode of said second input transistor to receive said second control signal and being in a conductive condition during thE presence of said second control signal to provide a second current signal from a second voltage source on an emitter electrode; a biasing-filtering connection means having a resistor connected between a connection terminal and the emitter electrodes of said first NPN transistor and said switching transistor at a junction point to receive said first and second current signals and being responsive to provide a voltage signal, said connection means having a capacitor connected to said terminal for establishing a rise and a fall slope of said voltage signal when said input signals change from said opposite to first and first to opposite polarity, respectively; a pair of oppositely poled clamping diodes connected between said junction point and a reference potential for receiving said voltage signal and being responsive during a succession of time intervals to provide a clamped signal having successively said rise slope, a first polarity clamped level, said fall slope, and an opposite polarity clamped level; first and second emitter-coupled NPN transistors forming a differential amplifier and having a base electrode of said first emitter-coupled NPN transistor connected to said junction point to receive said clamped signal to receive said first emitter-coupled transistor being operable in response to a first and an opposite polarity response level at its base electrode to bias said second emitter-coupled transistor into a conductive and a nonconductive condition, respectively, to provide a first and a second amplifier signal at its collector electrode, said clamping diodes providing clamped levels having a greater level than said response levels to control a delay time between said clamped and response levels; a second doublet having a second PNP transistor with an emitter electrode connected to a collector electrode of a second NPN transistor, said second PNP transistor having a base electrode connected to the collector electrode of said second emitter-coupled transistor to receive said first and second amplifier signals and being responsive to provide a second inverted signal to the base electrode of said second NPN transistor to bias said second NPN transistor into conductive and nonconductive conditions, respectively, to provide a first and a second gating signal on its emitter electrode; and an output NPN transistor having a base electrode connected to the emitter electrode of said second NPN transistor to receive said first and second gating signals and being in a conductive and nonconductive state in response to the presence of said first and second gating signals, respectively, to provide first and second output signals at a collector electrode, said output signals having different first and second voltage levels of like polarity.