← Back to Patent Explorer
US3312833A Expired / Lapsed US ⏱️ 0.0 years remaining

Amplifier parallel connected cathode follower output stage

Assignee: Beckman Coulter Inc
•
Filing: 1963-06-26
•
Granted: 1967-04-04
•
Expires: 1983-06-26
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

No abstract record available.

Inventors

  • 👤 Richard L Durrett

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-25 10:15
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/01; H03K5/02; H03G; H03G11/00

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 137 words
A CURRENT LIMITING OUTPUT STAGE FOR USE WITH AN AMPLIFIER COMPRISING FIRST AND SECOND TRANSISTORS OF OPPOSITE CONDUCTIVITY TYPES, EACH OF SAID TRANSISTORS INCLUDING A BASE, AND EMITTER AND COLLECTOR ELECTRODES, FIRST AND SECOND DIODES, INPUT AND OUTPUT TERMINALS, FIRST AND SECOND VOLTAGE TERMINALS ADAPTED TO BE CONNECTED TO SOURCES OF VOLTAGE, MEANS CONNECTING SAID INPUT TERMINAL WITH THE BASES OF SAID FIRST AND SECOND TRANSISTORS FOR APPLYING INPUT SIGNALS THERETO, MEANS CONNECTING THE COLLECTOR ELECTRODE OF SAID FIRST TRANSISTOR AND THE EMITTER ELECTRODE OF SAID SECOND TRANSISTOR WITH SAID FIRST VOLTAGE TERMINAL FOR SUPPLYING VOLTAGE TO SAID RESPECTIVE COLLECTOR AND EMITTER ELECTRODES THEREOF, MEANS CONNECTING SAID EMITTER ELECTRODES OF SAID FIRST TRANSISTOR AND SAID COLLECTOR ELECTRODE OF SAID SECOND TRANSISTOR WITH SAID SECOND VOLTAGE TERMINAL FOR SUPPLYING VOLTAGE TO THE RESPECTIVE EMITTER AND COLLECTOR ELECTRODES THEREOF,
Claim 2
Dependent Claim 137 words
A CURRENT LIMITING OUTPUT STAGE FOR USE WITH AN AMPLIFIER COMPRISING FIRST AND SECOND TRANSISTORS OF OPPOSITE CONDUCTIVITY TYPES, EACH OF SAID TRANSISTORS INCLUDING A BASE, AND EMITTER AND COLLECTOR ELECTRODES, FIRST AND SECOND DIODES, INPUT AND OUTPUT TERMINALS, FIRST AND SECOND VOLTAGE TERMINALS ADAPTED TO BE CONNECTED TO SOURCES OF VOLTAGE, MEANS CONNECTING SAID INPUT TERMINAL WITH THE BASES OF SAID FIRST AND SECOND TRANSISTORS FOR APPLYING INPUT SIGNALS THERETO, MEANS CONNECTING THE COLLECTOR ELECTRODE OF SAID FIRST TRANSISTOR AND THE EMITTER ELECTRODE OF SAID SECOND TRANSISTOR WITH SAID FIRST VOLTAGE TERMINAL FOR SUPPLYING VOLTAGE TO SAID RESPECTIVE COLLECTOR AND EMITTER ELECTRODES THEREOF, MEANS CONNECTING SAID EMITTER ELECTRODES OF SAID FIRST TRANSISTOR AND SAID COLLECTOR ELECTRODE OF SAID SECOND TRANSISTOR WITH SAID SECOND VOLTAGE TERMINAL FOR SUPPLYING VOLTAGE TO THE RESPECTIVE EMITTER AND COLLECTOR ELECTRODES THEREOF,

References Cited (Backward Citations)

US3064141A Cited
US2999925A Cited
US3172051A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1970-04-03 1970-10-03 1971-04-04 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1974-04-03 1974-10-03 1975-04-04 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1978-04-03 1978-10-03 1979-04-04 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag