US3942033A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Current mode logic circuit
Assignee: Motorola Solutions Inc
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Filing: 1974-05-02
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Granted: 1976-03-02
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Expires: 1994-05-02
Abstract
Abstract A current mode logic circuit providing AND/OR type functions wherein "0" voltage level changes and spikes are substantially eliminated without sacrificing switching speeds by omitting conventional emitter and collector-dotting between the logic input gates and an emitter-follower output stage. The input gates employ diode loads for generating reduced signal swings for driving the output gate. The output gate contains more devices than a single emitter-follower output stage, but the reduced signal swing and a push-pull drive mode for the output gate offsets any increased switching times due to the greater number of devices and thus achieves the overall objectives without any overall sacrifice in switching speed.
Inventors
- 👤 Frank J. Swiatowiec
- 👤 Ramachandra A. Rao
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 05:49
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/082; H03K19/086
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
210 words
A non-saturating logic circuit comprising: a. an M number of current mode input gates, each current mode input gate including a group of common collector node input logic switching transistors, and an interconnected reference voltage switching transistor; b. a first node logic connection, the reference voltage switching transistor associated with each of the M input gates being collector dotted to the first node logic connection; c. a current mode output gate, the output gate including an input switching transistor coupled to the first node logic connection and M interconnected selectively enabled reference transistors; d. a first load diode coupled to a reference voltage source means and to the first node logic connection for establishing a logic level signal swing at the input switching transistor of the output gate in response to the application of input logic signals to the input gates; e. each of the M reference transistors of the output gate being coupled, respectively, to one of the group of common collector node input logic switching transistors so as to be selectively enabled; and f. the output gate being responsive to a logic level signal swing at the first node logic connection and to the selective enabling of the M reference transistors for generating an output logic level signal.
Claim 2
Dependent Claim
210 words
A non-saturating logic circuit comprising: a. an M number of current mode input gates, each current mode input gate including a group of common collector node input logic switching transistors, and an interconnected reference voltage switching transistor; b. a first node logic connection, the reference voltage switching transistor associated with each of the M input gates being collector dotted to the first node logic connection; c. a current mode output gate, the output gate including an input switching transistor coupled to the first node logic connection and M interconnected selectively enabled reference transistors; d. a first load diode coupled to a reference voltage source means and to the first node logic connection for establishing a logic level signal swing at the input switching transistor of the output gate in response to the application of input logic signals to the input gates; e. each of the M reference transistors of the output gate being coupled, respectively, to one of the group of common collector node input logic switching transistors so as to be selectively enabled; and f. the output gate being responsive to a logic level signal swing at the first node logic connection and to the selective enabling of the M reference transistors for generating an output logic level signal.
Claim 3
Dependent Claim
51 words
A non-saturating logic circuit as in claim 1 further including: a. M conductive means for respectively connecting the base terminal of each of the M reference transistors of the output gate to a common collector node associated with the respective input gates for driving the output gate in a push-pull mode.
Claim 4
Dependent Claim
70 words
A non-saturating logic circuit as in claim 1 further comprising: a. M second nodes being constituted by the total number of common collector nodes for the M input gates; b. each of the M reference transistors of the output gate being respectively connected to one of the second nodes; and c. M second load diodes, each respectively coupled between one of the second nodes and the reference voltage source means.
Claim 5
Dependent Claim
50 words
A non-saturating logic circuit as in claim 3 further including: a. current source means coupled to the M input gates and the output gate for providing a plurality of current sources, each current source supplying a predetermined valued current flow to the M input gates and the output gate, respectively.
Claim 6
Dependent Claim
38 words
A non-saturating logic circuit as in claim 4 wherein: a. each of the input gates comprise an OR type logic gate; and b. the first node logic connection and the output gate comprise an AND type logic gate.
Claim 7
Dependent Claim
45 words
A non-saturating logic circuit as in claim 5 wherein: a. the output gate further includes an emitter follower transistor coupled to the collector terminal of the selectively enabled reference transistor of the output gate for supplying the output logic level signal at its emitter terminal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-03-02 | 1979-09-01 | 1980-03-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-03-02 | 1983-09-01 | 1984-03-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-03-02 | 1987-09-01 | 1988-03-02 | $7700.00 | Window Closed / Lapsed |