Patent US4535531A successfully refreshed from Google Patents.
US4535531A
Expired / Lapsed
US
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Method and resulting structure for selective multiple base width transistor structures
Assignee: International Business Machines Corp
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Filing: 1982-03-22
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Granted: 1985-08-20
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Expires: 2002-03-22
Abstract
Abstract A process is described which permits the fabrication of very narrow base width bipolar transistors in selected areas of an integrated circuit chip and bipolar transistors of wider base width on other selected areas of the same integrated circuit chip. The ability to selectively vary the transistor characteristics from one region of an integrated circuit chip to another provides a degree of freedom for design of integrated circuits which is valuable. The bipolar transistors on an integrated circuit chip are processed up to the point of emitter formation using conventional techniques. But, prior to the emitter formation, the base area which is to be the emitters of the selected region having the very narrow base transistors is dry etched using reactive ion etching. The existing silicon nitride/silicon dioxide layers with the emitter opening therein are used as the etching mask for this reactive ion etching procedure. Once the etching is completed to the desired depth, the normal processing is resumed to form the emitter and rest of the metallization.
Inventors
- 👤 Harsaran S. Bhatia
- 👤 Jack A. Dorler
- 👤 Santosh P. Gaur
- 👤 John S. Lechaton
- 👤 Joseph M. Mosley
- 👤 Gurumakonda R. Srinivasan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 08:23
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/60; H10D84/641; H10D84/642; H10D62/00; H10D62/10; H10D62/17; H10D62/177; H10D84/01; H10D84/0112; H10D84/02; H10D84/03; H10D84/038; H10P; H10P50/00; H10P50/20; H10P50/24; H10P50/242
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
228 words
A method for making an integrated circuit having two bipolar transistor types each having different operating speeds and amplification characteristics due to said transistor types being formed of different base widths, said method comprising: providing a monocrystalline silicon substrate having a pattern of regions of said silicon isolated from one another by a dielectric pattern on one major surface of said substrate; providing a subcollector region within said silicon and spaced from said major surface; forming a base region in at least certain of said regions of silicon down to said subcollector region wherein said base region has a surface concentration of more than about 1×10 18 atoms/cm 3 ; forming a block-out mask over said major surface in regions where said transistor type of lower said characteristics are desired; subjecting in areas uncovered by said block-out mask the said base regions wherein an emitter region is planned to be formed to reactive ion etching to form a depression having a depth between about 70 to 100 nanometers; removing said block-out mask; forming an emitter region in said etched portion of said base regions and in unetched base regions which were in areas covered by said block-out mask and heating said emitter region wherein the intrinsic base regions are formed of different base widths; and making electrical contact to each of the elements of said bipolar transistor types.
Claim 2
Independent Claim
228 words
A method for making an integrated circuit having two bipolar transistor types each having different operating speeds and amplification characteristics due to said transistor types being formed of different base widths, said method comprising: providing a monocrystalline silicon substrate having a pattern of regions of said silicon isolated from one another by a dielectric pattern on one major surface of said substrate; providing a subcollector region within said silicon and spaced from said major surface; forming a base region in at least certain of said regions of silicon down to said subcollector region wherein said base region has a surface concentration of more than about 1×10 18 atoms/cm 3 ; forming a block-out mask over said major surface in regions where said transistor type of lower said characteristics are desired; subjecting in areas uncovered by said block-out mask the said base regions wherein an emitter region is planned to be formed to reactive ion etching to form a depression having a depth between about 70 to 100 nanometers; removing said block-out mask; forming an emitter region in said etched portion of said base regions and in unetched base regions which were in areas covered by said block-out mask and heating said emitter region wherein the intrinsic base regions are formed of different base widths; and making electrical contact to each of the elements of said bipolar transistor types.
Claim 3
Dependent Claim
17 words
The method of claim 1 wherein the collector-base junction depth is between about 500 to 900 nanometers.
Claim 4
Dependent Claim
21 words
The method of claim 1 wherein the said base width for said etched transistors is between about 100 to 400 nanometers.
Claim 5
Dependent Claim
33 words
The method of claim 1 wherein the sides of said depression are substantially vertical without undercutting and the bottom of said depression is substantially planar from one vertical side to another vertical side.
Claim 6
Dependent Claim
41 words
The method of claim 1 wherein the depth of said depression is precisely monitored using a separate test wafer that has its silicon surface simultaneously etched while using laser light interferometer and the said etching is ended at the designated depth.
Claim 7
Dependent Claim
31 words
The method of claim 1 wherein the said reactive ion etching is accomplished using a mask composed layers of silicon dioxide and silicon nitride covering areas not desired to be etched.
Claim 8
Dependent Claim
26 words
The method of claim 6 wherein the said reactive ion etching ambient is argon and chlorine gas with a pressure less less than about 30 millitorr.
Claim 9
Dependent Claim
29 words
The method of claim 5 wherein said test wafer is composed of a silicon dioxide wafer having a polycrystalline silicon layer thereon and said laser is a He-Ne laser.
Claim 10
Dependent Claim
17 words
The method of claim 1 wherein said base doping is boron and said emitter doping is arsenic.
Claim 11
Dependent Claim
18 words
The method of claim 1 wherein said emitterbase junction depth is between about 350 nanometers to 500 nanometers.
Claim 12
Independent Claim
183 words
A method for making an integrated circuit having two bipolar transistor types each type having different base widths, said method comprising: providing a monocrystalline silicon substrate having a pattern of regions of said silicon isolated from one another by a dielectric pattern on one major surface of said substrate; providing a subcollector region within said silicon and spaced from said major surface; forming a base region in atleast certain of said regions of silicon down to said subcollector region wherein said base region has a surface concentration of more than about 1×10 18 atoms/cm 3 ; selectively etching certain of said base regions in areas where an emitter region is planned to form a depression having a depth between 70 to 100 nanometers, while leaving the remaining of said base regions intact; forming an emitter region in said etched portion of said base regions and in the base regions which were left intact and heating said emitter region wherein the intrinsic base regions are formed of different base widths; and making electrical contact to each of the elements of said bipolar transistor types.
Claim 13
Independent Claim
183 words
A method for making an integrated circuit having two bipolar transistor types each type having different base widths, said method comprising: providing a monocrystalline silicon substrate having a pattern of regions of said silicon isolated from one another by a dielectric pattern on one major surface of said substrate; providing a subcollector region within said silicon and spaced from said major surface; forming a base region in atleast certain of said regions of silicon down to said subcollector region wherein said base region has a surface concentration of more than about 1×10 18 atoms/cm 3 ; selectively etching certain of said base regions in areas where an emitter region is planned to form a depression having a depth between 70 to 100 nanometers, while leaving the remaining of said base regions intact; forming an emitter region in said etched portion of said base regions and in the base regions which were left intact and heating said emitter region wherein the intrinsic base regions are formed of different base widths; and making electrical contact to each of the elements of said bipolar transistor types.
Claim 14
Dependent Claim
17 words
The method of claim 11 wherein the collector-base junction depth is between about 500 to 900 nanometers.
Claim 15
Dependent Claim
21 words
The method of claim 11 wherein the said base width for said etched transistors is between about 100 to 400 nanometers.
Claim 16
Dependent Claim
18 words
The method of claim 11 wherein said emitter base junction depth is between about 350 to 500 nanometers.
Claim 17
Dependent Claim
25 words
The method of claim 11 wherein said selective etching is accomplished by reactive ion etching using a mask covering areas not desired to be etched.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-08-19 | 1989-02-18 | 1989-08-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-08-19 | 1993-02-18 | 1993-08-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-08-19 | 1997-02-18 | 1997-08-20 | $7700.00 | Window Closed / Lapsed |