Programmable read only memory integrated circuit device

Claim 1

A read only memory integrated circuit device comprising a semiconductor substrate, a memory array including a column conductor and a first group of transistors serving as memory elements integrated on a surface of said semiconductor substrate, each of said transistors having emitter, base, and collector regions, said emitter region being connected to said column conductor, said base region being located below said emitter region and being at a floating potential, said collector region being located below said base region and forming the row of said memory array, and programming means including a second group of transistors integrated on said surface of said semiconductor substrate for applying a voltage between the emitter and collector regions of at least one selected transistor of said first group of transistors to reverse bias the emitter-base junction of said selected transistor, thereby to cause a short-circuit of said emitter-base junction, the base width of said first group of transistors exceeding that of said second group of transistors.