US3810123A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Monolithic storage multi-emitter transistors with different width bases
Assignee: International Business Machines Corp
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Filing: 1972-06-29
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Granted: 1974-05-07
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Expires: 1992-06-29
Abstract
Abstract A monolithic storage matrix having cells formed of multi-emitter transistors in which one emitter of each transistor forms part of the storage circuit and the other emitter of each transistor is coupled to the accessing and retrieval circuits. The transistors portions for storage are formed with bases of a given width and the transistors portions coupled to the accessing and retrieving circuits have a lesser width so that short access times are obtained while the stability of the storage circuit is maintained.
Inventors
- 👤 U Baitinger
- 👤 K Najmann
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 14:54
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/60; H10D84/641; H10D84/642; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/411; G11C11/4116; H10B; H10B10/00; H10B10/10; Y; Y10; Y10S; Y10S148/00; Y10S148/037; Y10S148/085; Y10S148/145
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
126 words
An integrated monolithic storage array, comprising: a plurality of storage cells arranged in matrix form on a semiconductor substrate, each of said cells being formed of a pair of multi-emitter cross-coupled transistors, each said transistor including a storage portion and a control portion; accessing means connected to the emitters of said control portions for writing into and retrieving information from said cells; first means within the storage portion of each of said transistors for amplifying current through said storage portions to a first level when said storage portions are operative; and second means within said control portions of said transistors for amplifying current through said control portions to a second level greater than the first level when said control portions are accessed by said accessing means.
Claim 2
Dependent Claim
126 words
An integrated monolithic storage array, comprising: a plurality of storage cells arranged in matrix form on a semiconductor substrate, each of said cells being formed of a pair of multi-emitter cross-coupled transistors, each said transistor including a storage portion and a control portion; accessing means connected to the emitters of said control portions for writing into and retrieving information from said cells; first means within the storage portion of each of said transistors for amplifying current through said storage portions to a first level when said storage portions are operative; and second means within said control portions of said transistors for amplifying current through said control portions to a second level greater than the first level when said control portions are accessed by said accessing means.
Claim 3
Dependent Claim
46 words
The array of claim 1, wherein the first means comprises a base region of a first width for said storage portions and the second means comprises a base region of a second width for said control portions, said second width being less than said first width.
Claim 4
Dependent Claim
107 words
A storage cell, comprising a pair of multi-emitter cross coupled transistors, each said transistor including a storage portion and a control portion; accessing means connected to the emitter of said control portions for writing into and retrieving information from said cells; first means within the storage portions of said transistors for amplifying the current through said storage portions to a first level when operative, and second means within said control portions of said transistors and coupled to said accessing means for amplifying the current through said control portions to a second level greater than the first level when said control portions are accessed by said accessing means.
Claim 5
Dependent Claim
107 words
A storage cell, comprising a pair of multi-emitter cross coupled transistors, each said transistor including a storage portion and a control portion; accessing means connected to the emitter of said control portions for writing into and retrieving information from said cells; first means within the storage portions of said transistors for amplifying the current through said storage portions to a first level when operative, and second means within said control portions of said transistors and coupled to said accessing means for amplifying the current through said control portions to a second level greater than the first level when said control portions are accessed by said accessing means.
Claim 6
Dependent Claim
48 words
The array of claim 3, wherein the first means comprises a base for region of a first width for said storage portions and the second means comprises a base for region of a second width for said control portions, said second width being less than said first width.
References Cited (Backward Citations)
US3662351A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-05-06 | 1977-11-05 | 1978-05-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-05-06 | 1981-11-05 | 1982-05-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-05-06 | 1985-11-05 | 1986-05-07 | $7700.00 | Window Closed / Lapsed |