US4030954A
Expired / Lapsed
US
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Method of manufacturing a semiconductor integrated circuit device
Assignee: Hitachi Ltd
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Filing: 1975-09-30
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Granted: 1977-06-21
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Expires: 1995-09-30
Abstract
Abstract A method of manufacturing a semiconductor integrated circuit device including N-P-N transistors is characterized in that a base region of at least one of the N-P-N transistors is partially etched and removed with chemicals, thus to be formed with a depression, and that an emitter region opposite in the conductivity type to the base region is formed in the base region beneath the depression, whereby the at least one N-P-N transistor is made higher in the current gain h FE than the other N-P-N transistors being the main constituents of the integrated circuit device.
Inventors
- 👤 Noboru Horie
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 10:19
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/60; H10D84/641; H10D84/642; H10D62/00; H10D62/10; H10D62/17; H10D62/177; H10D84/01; H10D84/0112; H10D84/02; H10D84/03; H10D84/038
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
154 words
In a method of manufacturing at least two transistors, having current gains different from each other, in a semiconductor integrated circuit, the improvement comprising the steps of a. providing a semiconductor substrate having at least first and second collector regions each having a first conductivity type, electrically isolated from each other, respectively extending to a principal surface of the semiconductor substrate, b. diffusing an impurity of a second conductivity type, opposite to said first conductivity type, at the same time in said first and second collector regions, from said principal surface, to form first and second base regions in said first and second collector regions, respectively, c. partially removing a surface portion of said first base region to form a depression therein, and d. diffusing an impurity of said first conductivity type in said first base region beneath said depression and said second region from said principal surface, to form emitter regions therein, respectively.
Claim 2
Dependent Claim
154 words
In a method of manufacturing at least two transistors, having current gains different from each other, in a semiconductor integrated circuit, the improvement comprising the steps of a. providing a semiconductor substrate having at least first and second collector regions each having a first conductivity type, electrically isolated from each other, respectively extending to a principal surface of the semiconductor substrate, b. diffusing an impurity of a second conductivity type, opposite to said first conductivity type, at the same time in said first and second collector regions, from said principal surface, to form first and second base regions in said first and second collector regions, respectively, c. partially removing a surface portion of said first base region to form a depression therein, and d. diffusing an impurity of said first conductivity type in said first base region beneath said depression and said second region from said principal surface, to form emitter regions therein, respectively.
Claim 3
Dependent Claim
25 words
The improvement according to claim 1, wherein said step of removing comprises the step of selectively etching said surface portion of said first base region.
Claim 4
Dependent Claim
33 words
The improvement according to claim 1, wherein said step of selectively etching comprises selectively masking the surface of the said first base region and chemically etching the surface of said first base region.
Claim 5
Independent Claim
151 words
A method of manufacturing a semiconductor integrated circuit device having first and second transistors with differing current gains comprising the steps of: a. forming first and second base regions of semiconductor material of a first conductivity type in separated and electrically isolated collector regions of a semiconductor substrate of a second conductivity type, opposite said first conductivity type, so that said base regions extend to a first principal surface of said substrate in which said collector regions are respectively provided; b. partially removing semiconductor material from a selected surface portion of said first base region to form a depression therein; c. forming a first emitter region of semiconductor material of said second conductivity type in a selected portion of said first base region beneath the depression therein; and d. forming a second emitter region of semiconductor material of said second conductivity type in a selected portion of said second base region.
Claim 6
Independent Claim
151 words
A method of manufacturing a semiconductor integrated circuit device having first and second transistors with differing current gains comprising the steps of: a. forming first and second base regions of semiconductor material of a first conductivity type in separated and electrically isolated collector regions of a semiconductor substrate of a second conductivity type, opposite said first conductivity type, so that said base regions extend to a first principal surface of said substrate in which said collector regions are respectively provided; b. partially removing semiconductor material from a selected surface portion of said first base region to form a depression therein; c. forming a first emitter region of semiconductor material of said second conductivity type in a selected portion of said first base region beneath the depression therein; and d. forming a second emitter region of semiconductor material of said second conductivity type in a selected portion of said second base region.
Claim 7
Dependent Claim
15 words
A method according to claim 4, wherein steps (c) and (d) are carried out simultaneously.
Claim 8
Dependent Claim
33 words
A method according to claim 4, wherein steps (c) and (d) include the simultaneous introduction of impurities of said second conductivity type into the selected portions of said first and second base regions.
Claim 9
Dependent Claim
58 words
A method according to claim 6, wherein step (b) comprises selectively etching said first base region to a prescribed depth beneath said selected surface portion thereof to thereby reduce the base width of said first transistor as compared to that of said second transistor, whereby the current gain of said first transistor exceeds that of said second transistor.
Claim 10
Dependent Claim
33 words
A method according to claim 7, wherein said step of selectively etching comprises selectively masking the surface of the said first base region and chemically etching the surface of said first base region.
References Cited (Backward Citations)
US3808058A
Cited
US3891469A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-06-20 | 1980-12-20 | 1981-06-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-06-20 | 1984-12-20 | 1985-06-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-06-20 | 1988-12-20 | 1989-06-21 | $7700.00 | Window Closed / Lapsed |