US4455567A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Polycrystalline semiconductor resistor having a noise reducing field plate
Assignee: Raytheon Co
•
Filing: 1981-11-27
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Granted: 1984-06-19
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Expires: 2001-11-27
Abstract
Abstract A polycrystalline silicon field plate underlies a polycrystalline silicon resistor and is heavily doped so that it is virtually a conductor while an aluminum field plate overlies the polycrystalline silicon resistor. Electrical potentials are applied to the polycrystalline field plate and the aluminum field plate, the potentials being selected so that an electric field is created at the boundary between the polycrystalline semiconductor resistor and the surrounding dielectric layer, the electric field forcing charge carriers in the resistor away from the boundary and toward a central region of the resistor. As a result, surface state noise in the resistor is significantly reduced.
Inventors
- 👤 Joseph Y. M. Lee
- 👤 Gary E. Grimm
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 16:23
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/40; H10D1/47; H10D1/43; H10D88/00
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
101 words
A low noise polycrystalline semiconductor resistor, comprising: a semiconductive substrate including an overlying dielectric layer; a polycrystalline semiconductor resistor formed in said dielectric layer; an insulated polycrystalline semiconductor field plate formed in said dielectric layer between said resistor and said substrate; an insulated field plate overlying said polycrystalline semiconductor resistor; and means for applying like potentials to said field plates suitable to repel charge carriers in said polycrystalline semiconductor resistor away from the upper and lower boundaries between said resistor and said dielectric layer and toward the core of said resistor so as to reduce noise in said polycrystalline semiconductor resistor.
Claim 2
Dependent Claim
101 words
A low noise polycrystalline semiconductor resistor, comprising: a semiconductive substrate including an overlying dielectric layer; a polycrystalline semiconductor resistor formed in said dielectric layer; an insulated polycrystalline semiconductor field plate formed in said dielectric layer between said resistor and said substrate; an insulated field plate overlying said polycrystalline semiconductor resistor; and means for applying like potentials to said field plates suitable to repel charge carriers in said polycrystalline semiconductor resistor away from the upper and lower boundaries between said resistor and said dielectric layer and toward the core of said resistor so as to reduce noise in said polycrystalline semiconductor resistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-06-19 | 1987-12-19 | 1988-06-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-06-19 | 1991-12-19 | 1992-06-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-06-19 | 1995-12-19 | 1996-06-19 | $7700.00 | Window Closed / Lapsed |