US4234889A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Metal-to-moat contacts in N-channel silicon gate integrated circuits using discrete second-level polycrystalline silicon
Assignee: Texas Instruments Inc
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Filing: 1977-05-31
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Granted: 1980-11-18
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Expires: 1997-05-31
Abstract
Abstract A double-level polycrystalline silicon structure for an N-channel MOS integrated circuit is disclosed including a metal interconnect level. Contact between the metal interconnect level and N+ diffused moat areas is made through discrete second-level polysilicon areas which reduce the step from metal level to moat level, thus increasing yields. Also, connections from the metal level to the first level polysilicon are made using a discrete area of second level polysilicon to minimize the step.
Inventors
- 👤 Joseph H. Raymond, Jr.
- 👤 Jih-Chang Lien
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 14:46
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/44; H10W20/4451; H10B; H10B10/00; H10B10/15; H10W20/435
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
308 words
A contact and interconnection arrangement for a semiconductor integrated circuit of the type having circuit elements formed at a face of a semiconductor body, a plurality of levels of contacts and electrode areas and interconnections at said face of the body, the levels including at least one level of polycrystalline silicon and one of metallization on the face as well as elongated regions of monocrystalline semiconductor material in the face, said elongated regions being of opposite conductivity-type and more heavily doped than surrounding material in said face, a first insulating layer on said face between the semiconductor material and said at least one level of polycrystalline silicon and a second insulating layer on said face between said at least one level of polycrystalline silicon and said level of metallization, the improvement wherein: a connection between a contact part of the level of metallization and a contact area on a part of an elongated region of the semiconductor material includes a discrete area of one of the levels of polycrystalline silicon, said discrete area being substantially uniformly doped with impurity between said contact part of the level of metallization and said contact area of said elongated region, said discrete area being solely for the purpose of making electrical connection from said contact part of the level of metallization and said contact area and not being a part of or being connected to said circuit elements except through said contact part of the level of metallization and said contact area on said part of said elongated region of semiconductor material, said discrete area contacting said contact area through a first aperature in said first insulating layer, said first aperature being smaller than said discrete area, said contact part contacting said discrete area through a second aperature in said second insulating layer, said second aperature being smaller than said contact part.
Claim 2
Dependent Claim
308 words
A contact and interconnection arrangement for a semiconductor integrated circuit of the type having circuit elements formed at a face of a semiconductor body, a plurality of levels of contacts and electrode areas and interconnections at said face of the body, the levels including at least one level of polycrystalline silicon and one of metallization on the face as well as elongated regions of monocrystalline semiconductor material in the face, said elongated regions being of opposite conductivity-type and more heavily doped than surrounding material in said face, a first insulating layer on said face between the semiconductor material and said at least one level of polycrystalline silicon and a second insulating layer on said face between said at least one level of polycrystalline silicon and said level of metallization, the improvement wherein: a connection between a contact part of the level of metallization and a contact area on a part of an elongated region of the semiconductor material includes a discrete area of one of the levels of polycrystalline silicon, said discrete area being substantially uniformly doped with impurity between said contact part of the level of metallization and said contact area of said elongated region, said discrete area being solely for the purpose of making electrical connection from said contact part of the level of metallization and said contact area and not being a part of or being connected to said circuit elements except through said contact part of the level of metallization and said contact area on said part of said elongated region of semiconductor material, said discrete area contacting said contact area through a first aperature in said first insulating layer, said first aperature being smaller than said discrete area, said contact part contacting said discrete area through a second aperature in said second insulating layer, said second aperature being smaller than said contact part.
Claim 3
Dependent Claim
31 words
A device according to claim 1 wherein said discrete area is a part of a second level of polycrystalline silicon which at least partially overlies a first level of polycrystalline silicon.
Claim 4
Dependent Claim
29 words
A device according to claim 2 wherein the circuit elements include N-channel silicon-gate MOS transistors and the first level of polycrystalline silicon forms gate electrodes of the MOS transistors.
Claim 5
Dependent Claim
34 words
A device according to claim 3 wherein the second level of polycrystalline silicon extends across parts of the heavily-doped semiconductor material and the first level of polycrystalline silicon does not overly heavily-doped semiconductor material.
Claim 6
Dependent Claim
42 words
A device according to claim 4 wherein a thick insulating coating surrounds the heavily-doped semiconductor material on the face and another thick insulating coating is provided between the second level of polycrystalline silicon and the level of metallization except at said connection.
Claim 7
Dependent Claim
244 words
A contact arrangement for a semiconductor integrated circuit of the type having circuit elements formed at a face of a semiconductor body, at least one of the circuit elements having a region of monocrystalline semiconductor material in the face, said region being of opposite conductivity-type and more heavily doped than surrounding semiconductor material in the face, and a metal strip overlying said face, a part of the metal strip making electrical connection to said region at a contact area, the improvement comprising a layer of polycrystalline semiconductor material directly overlying said region at said contact area and interposed between said part of the metal strip and said region to be included in the electrical connection, said layer being substantially uniformly doped with impurity between said part of the metal strip and said contact area, said layer being solely for the purpose of making electrical connection from said region and not being a portion of any electrical circuit elements, the metal strip not contacting said region except through said layer, a first insulating coating between said face and said layer of polycrystalline semiconductor material with a first aperature in said first coating smaller than said layer, said layer contacting said contact area only through said first aperature, a second insulating coating between said layer and said metal strip with a second aperature in said second coating smaller than said part of the metal strip, said metal strip contacting said layer only through said second aperature.
Claim 8
Dependent Claim
244 words
A contact arrangement for a semiconductor integrated circuit of the type having circuit elements formed at a face of a semiconductor body, at least one of the circuit elements having a region of monocrystalline semiconductor material in the face, said region being of opposite conductivity-type and more heavily doped than surrounding semiconductor material in the face, and a metal strip overlying said face, a part of the metal strip making electrical connection to said region at a contact area, the improvement comprising a layer of polycrystalline semiconductor material directly overlying said region at said contact area and interposed between said part of the metal strip and said region to be included in the electrical connection, said layer being substantially uniformly doped with impurity between said part of the metal strip and said contact area, said layer being solely for the purpose of making electrical connection from said region and not being a portion of any electrical circuit elements, the metal strip not contacting said region except through said layer, a first insulating coating between said face and said layer of polycrystalline semiconductor material with a first aperature in said first coating smaller than said layer, said layer contacting said contact area only through said first aperature, a second insulating coating between said layer and said metal strip with a second aperature in said second coating smaller than said part of the metal strip, said metal strip contacting said layer only through said second aperature.
References Cited (Backward Citations)
US3519901A
Cited
US3576478A
Cited
US3667008A
Cited
US3792384A
Cited
US3881242A
Cited
US4041518A
Cited
US3936865A
Cited
US3852799A
Cited
US4042953A
Cited
US3902188A
Cited
UST964009I4
Cited
US4146902A
Cited
US4055444A
Cited
US4110776A
Cited
US4125854A
Cited
US4112509A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-11-18 | 1984-05-19 | 1984-11-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-11-18 | 1988-05-19 | 1988-11-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-11-18 | 1992-05-19 | 1992-11-18 | $7700.00 | Window Closed / Lapsed |