Method of making FET containing stacked gates

Claim 1

In a method for fabricating an integrated circuit containing an array of FETs and the associated, addressing, decoding and sensing circuits wherein individual FETs of the array include a floating gate and a control gate in a stacked relationship with each other and having electrical insulator between the floating and control gates which comprises: A. delineating predetermined insulating regions above or recessed into the substrate to provide isolating field regions between FETs of the array; B. then delineating a first layer of gate-forming material employing the same lithographic mask to provide a floating gate and a control gate which are self-aligned with each other in all lateral directions, and to provide etched regions which are to be subsequently doped for forming source and drain regions self-aligned in the length dimensions with respect to both of said floating and control gates; C. then thermally diffusing or ion-implanting active impurities into predetermined regions of the semiconductive substrate beneath the etched regions to provide source and drain regions which are self-aligned with respect to said floating and control gates; D. then providing insulating layer; E. then delineating contact holes to source and drain regions; and F. then delineating a metallic-type high-conductivity electrical interconnection pattern that makes electrical connection to the control gates in the array of FETs and to FET sources and drains.