US4096509A
Expired / Lapsed
US
⏱️ 0.0 years remaining
MNOS memory transistor having a redeposited silicon nitride gate dielectric
Assignee: United States Department of the Air Force
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Filing: 1976-07-22
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Granted: 1978-06-20
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Expires: 1996-07-22
Abstract
Abstract A processing technique utilizing two separate silicon nitride depositions (one to form the memory regions and the second to form the nonmemory regions) is employed to provide a radiation hard drain source protected memory transistor. The amount of silicon dioxide used in the nonmemory regions is also minimized. A typical device comprises a mesa etched from a silicon-on-sapphire (SOS) wafer into which P+ source and drain regions are implanted. A 100 A layer of silicon dioxide and a second 1000 A layer of nonmemory silicon nitride covers the mesa and the two layers are etched to define a substrate gate window. The gate window is covered by a 25 A layer of tunneling oxide A final 500 A layer of memory silicon nitride covers the mesa structure. Contact windows are etched to accommodate source, drain and gate interconnect electrodes.
Inventors
- 👤 Franklyn C. Blaha
- 👤 James R. Cricchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 11:35
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/60; H10D64/66; H10D64/68; H10D64/681; H10D64/685; H10D30/00; H10D30/60; H10D30/67; H10D30/6704; H10D30/6729; H10D30/6737; H10D30/6739; H10D30/6758; H10D30/6759; H10D30/69; H10D64/693; H10D86/00; H10D86/01; H10D86/03; Y; Y10; Y10S; Y10S148/00; Y10S148/018; Y10S148/02; Y10S148/082; Y10S148/15
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
161 words
A radiation hardened MNOS memory transistor comprising a substrate of electrically insulating material, a mesa of semiconductor material deposited on the surface thereof, a source region formed by P+ diffusions into a portion of said mesa adjacent one edge thereof, a drain region formed by P+ diffusions into a portion of said mesa adjacent the edge thereof opposite said source region, said source and drain regions in part defining a substrate gate region therebetween, a layer of silicon dioxide covering said substrate gate region and portions of said source and drain regions, a portion of said silicon dioxide layer in the vicinity of said substrate gate region being removed to define a gate window, a layer of tunneling oxide covering said gate window, a layer of non-memory silicon nitride covering said silicon dioxide layer, a layer of memory silicon nitride covering said non-memory silicon nitride layer and said tunneling oxide layer, a source electrode, a drain electrode, and a gate electrode.
Claim 2
Dependent Claim
161 words
A radiation hardened MNOS memory transistor comprising a substrate of electrically insulating material, a mesa of semiconductor material deposited on the surface thereof, a source region formed by P+ diffusions into a portion of said mesa adjacent one edge thereof, a drain region formed by P+ diffusions into a portion of said mesa adjacent the edge thereof opposite said source region, said source and drain regions in part defining a substrate gate region therebetween, a layer of silicon dioxide covering said substrate gate region and portions of said source and drain regions, a portion of said silicon dioxide layer in the vicinity of said substrate gate region being removed to define a gate window, a layer of tunneling oxide covering said gate window, a layer of non-memory silicon nitride covering said silicon dioxide layer, a layer of memory silicon nitride covering said non-memory silicon nitride layer and said tunneling oxide layer, a source electrode, a drain electrode, and a gate electrode.
Claim 3
Dependent Claim
32 words
A radiation hardened MNOS memory transistor as defined in claim 1 wherein said substrate of electrically insulating material consists of sapphire and said mesa of semiconductor material consists of N type silicon.
Claim 4
Dependent Claim
55 words
A radiation hardened MNOS memory transistor as defined in claim 2 wherein said layer of silicon dioxide is substantially 100 A thick, said layer of non-memory silicon nitride is substantially 1000 A thick, said layer of tunneling oxide is substantially 25 A thick and said layer of memory silicon nitride is substantially 500 A thick.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-06-19 | 1981-12-19 | 1982-06-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-06-19 | 1985-12-19 | 1986-06-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-06-19 | 1989-12-19 | 1990-06-20 | $7700.00 | Window Closed / Lapsed |