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US3958266A Expired / Lapsed US ⏱️ 0.0 years remaining

Deep depletion insulated gate field effect transistors

Assignee: RCA Corp
•
Filing: 1974-04-19
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Granted: 1976-05-18
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Expires: 1994-04-19
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Abstract

Abstract A deep depletion insulated gate field effect transistor is made in a silicon layer on a sapphire substrate, so that its threshold voltage is relatively independent of the thickness of the silicon layer. The silicon layer has two parts, namely, a lower part adjacent to the sapphire substrate which is relatively lightly doped, and an upper part, preferably formed by ion implantation, having a doping concentration on the order of about 2 × 10 15 atoms/cm 3 .

Inventors

  • 👤 Terry George Athanas

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 04:19
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/67; H10D30/6758; H10D30/6759; H10D30/637; H10D86/00; H10D86/01; H10D86/03; H10D99/00; Y; Y10; Y10S; Y10S148/00; Y10S148/053; Y10S148/15

Claims Analysis

Total Claims: 3
Claim 1
Independent Claim 221 words
An integrated circuit device comprising: an insulating substrate, a plurality of thin, layerlike bodies of monocrystalline semiconductive material, all initially of the same given type conductivity on said substrate, and each having a surface substantially parallel to the surface of the substrate, and means including at least one of said bodies forming an insulated gate field effect transistor operable in the deep-depletion mode, said means comprising spaced source and drain regions of said given type conductivity in said one body defining therebetween a conduction channel region, an insulating layer on said surface of said one body adjacent to said channel region and gate electrode means on said insulating layer, said channel region having a first part adjacent to said surface having a thickness less than that of said body, having said given type conductivity and having a conductivity such that a predetermined voltage applied to said gate electrode, relative to that applied to said body, will effectively deplete said first part of mobile charge carriers, said channel region also having a second part beneath said first part, extending throughout the remainder of the thickness of said channel region, having said given type conductivity and having a conductivity less than that of said first part such that a voltage substantially less than said predetermined voltage will effectively deplete it of charge carriers.
Claim 2
Dependent Claim 221 words
An integrated circuit device comprising: an insulating substrate, a plurality of thin, layerlike bodies of monocrystalline semiconductive material, all initially of the same given type conductivity on said substrate, and each having a surface substantially parallel to the surface of the substrate, and means including at least one of said bodies forming an insulated gate field effect transistor operable in the deep-depletion mode, said means comprising spaced source and drain regions of said given type conductivity in said one body defining therebetween a conduction channel region, an insulating layer on said surface of said one body adjacent to said channel region and gate electrode means on said insulating layer, said channel region having a first part adjacent to said surface having a thickness less than that of said body, having said given type conductivity and having a conductivity such that a predetermined voltage applied to said gate electrode, relative to that applied to said body, will effectively deplete said first part of mobile charge carriers, said channel region also having a second part beneath said first part, extending throughout the remainder of the thickness of said channel region, having said given type conductivity and having a conductivity less than that of said first part such that a voltage substantially less than said predetermined voltage will effectively deplete it of charge carriers.
Claim 3
Dependent Claim 81 words
An integrated circuit device as defined in claim 1, wherein: said substrate is monocrystalline sapphire, said layerlike bodies are monocrystalline silicon and said spaced regions each extend throughout the thickness of said body, said first part contains conductivity modifiers in a substantial portion thereof having a density on the order of 10 16 modifiers/cm 3 , and said second part contains conductivity modifiers having a density on the order of 10 13 modifiers/cm 3 throughout a large portion of its volume.

References Cited (Backward Citations)

US3653978A Cited
US3789504A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1979-05-18 1979-11-17 1980-05-18 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1983-05-18 1983-11-17 1984-05-18 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1987-05-18 1987-11-17 1988-05-18 $7700.00 Window Closed / Lapsed

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