Patent US2900090A successfully refreshed from Google Patents.
US3728784A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Fabrication of semiconductor devices
Assignee: Monsanto Co
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Filing: 1971-04-15
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Granted: 1973-04-24
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Expires: 1991-04-15
Abstract
Abstract The disclosure herein pertains to methods for fabricating planar, discrete or monolithic arrays of semiconductor devices, particularly light-emitting diodes and arrays thereof. The disclosure more particularly concerns diffusion processes to form controlled regions of P-type conductivity in N-type conductivity semiconductors.
Inventors
- 👤 J Schmidt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 04:47
CPC Classifications
H; H10; H10W; H10W74/00; H10W74/40; H10W74/43; H10H; H10H20/00; H10H20/80; H10P; H10P32/00; H10P32/10; H10P32/14; H10P32/17; H10P32/174; H10P95/00; H10W72/00; H10W72/90; H10W72/50; H10W72/531; H10W72/536; H10W72/59
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
257 words
Process for fabricating semiconductor devices which comprises: a. providing a semiconductor substrate; b. applying to the front surface of said substrate a laminated impurity diffusion masking system consisting of a layer of Si3N4 sandwiched between layers of SiO2; c. etching diffusion windows through said diffusion masking system to expose diffusion surfaces of said substrate; d. depositing a layer of SiO2 over the back surface of said substrate and another layer of SiO2 over the front of said substrate; e. heat treating the structure of step (d); f. depositing a layer of impurity oxide onto said layer of SiO2 deposited on the front surface of said substrate in step (d); g. depositing a layer of SiO2 onto said layer of impurity oxide; h. heating the structure of step (g) to diffuse impurities from said impurity oxide into said semiconductor; i. etching from the structure of step (h) the oxide layers deposited in steps (d), (f) and (g); j. depositing a layer of SiO2 over the front surface of said substrate; k. etching windows through the SiO2 layer deposited in step (j) to expose selected areas of said substrate previously diffused with impurities by step (h); l. diffuse an additional amount of said impurities into said selected areas of said substrate; m. applying ohmic contact material in the desired pattern to the front surface of said substrate and in contact therewith at said selected areas; n. applying ohmic contact to the back surface of said substrate; o. affixing electrical leads to an external circuit and p. encapsulating the device.
Claim 2
Dependent Claim
257 words
Process for fabricating semiconductor devices which comprises: a. providing a semiconductor substrate; b. applying to the front surface of said substrate a laminated impurity diffusion masking system consisting of a layer of Si3N4 sandwiched between layers of SiO2; c. etching diffusion windows through said diffusion masking system to expose diffusion surfaces of said substrate; d. depositing a layer of SiO2 over the back surface of said substrate and another layer of SiO2 over the front of said substrate; e. heat treating the structure of step (d); f. depositing a layer of impurity oxide onto said layer of SiO2 deposited on the front surface of said substrate in step (d); g. depositing a layer of SiO2 onto said layer of impurity oxide; h. heating the structure of step (g) to diffuse impurities from said impurity oxide into said semiconductor; i. etching from the structure of step (h) the oxide layers deposited in steps (d), (f) and (g); j. depositing a layer of SiO2 over the front surface of said substrate; k. etching windows through the SiO2 layer deposited in step (j) to expose selected areas of said substrate previously diffused with impurities by step (h); l. diffuse an additional amount of said impurities into said selected areas of said substrate; m. applying ohmic contact material in the desired pattern to the front surface of said substrate and in contact therewith at said selected areas; n. applying ohmic contact to the back surface of said substrate; o. affixing electrical leads to an external circuit and p. encapsulating the device.
Claim 3
Dependent Claim
11 words
Process according to claim 1 wherein said impurity oxide is ZnO.
Claim 4
Dependent Claim
26 words
Process according to claim 2 wherein sAid semiconductor substrate is of N-type conductivity and is selected from the group consisting of III-V compounds and mixtures thereof.
Claim 5
Dependent Claim
22 words
Process according to claim 3 wherein said semiconductor substrate is GaAs1 XPX, where X is a number from zero to one inclusive.
Claim 6
Dependent Claim
15 words
Process according to claim 4 wherein X equals one and said semiconductor substrate is GaAs.
Claim 7
Dependent Claim
19 words
Process according to claim 5 wherein the semiconductor device is a light-emitting device and is encapsulated in transparent material.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-04-23 | 1976-10-23 | 1977-04-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-04-23 | 1980-10-23 | 1981-04-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-04-23 | 1984-10-23 | 1985-04-24 | $7700.00 | Window Closed / Lapsed |