US3859642A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Random access memory array of hysteresis loop capacitors
Assignee: AT&T Inc
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Filing: 1973-04-05
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Granted: 1975-01-07
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Expires: 1993-04-05
Abstract
Abstract A rectangular array of metal-insulator-semiconductor (MIS) capacitors is utilized in a random access memory array apparatus. Each MIS capacitor has a double-insulator layer, with a consequent hysteresis loop characteristic of differential capacitances versus voltage. Write-in of information is accomplished by the application of suitable crosspoint voltages to the array; whereas readout of information (stored in a particular crosspoint capacitor) is accomplished by means of voltage biasing all the capacitors in the array to a sufficiently large negative voltage (lower branch of all hysteresis loops) and then applying a ''''zero'''' voltage bias pulse (i.e., within hysteresis loops) to the particular crosspoint capacitor, and also applying a positive voltage pulse to the same crosspoint capacitor during said zero bias pulse. The electrical current response of the crosspoint capacitor to the positive voltage pulse is a measure of the capacitance of the crosspoint capacitor and hence of its memory state.
Inventors
- 👤 Jerry Mar
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 05:42
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0466
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
198 words
A memory storage apparatus which comprises a. an array of row and column electrically conductive lines forming a plurality of intersecting crosspoints; b. an equal plurality of substantially identical two-terminal capacitor memory cells, each cell characterized by a single-valued portion and a double-valued portion hysteresis loop of differential capacitance versus voltage, and each said cell being connected across a different crosspoint at which one terminal of the cell is connected to a roW line and the other terminal of the cell is connected to a column line; and c. circuit means for applying a first voltage pulse to a selected row line such that only one or more of those capacitor elements having a terminal connected to the selected row line are biased into a double-valued portion of their hysteresis loops, the others being in a single-valued portion, and for applying a second voltage singal to the selected row line within the time duration of and superimposed on the first voltage pulse, whereby the electrical current response to said second voltage signal of at least one of the capacitors having a terminal connected to the selected row line is indicative of the respective memory state of this capaccitor.
Claim 2
Dependent Claim
198 words
A memory storage apparatus which comprises a. an array of row and column electrically conductive lines forming a plurality of intersecting crosspoints; b. an equal plurality of substantially identical two-terminal capacitor memory cells, each cell characterized by a single-valued portion and a double-valued portion hysteresis loop of differential capacitance versus voltage, and each said cell being connected across a different crosspoint at which one terminal of the cell is connected to a roW line and the other terminal of the cell is connected to a column line; and c. circuit means for applying a first voltage pulse to a selected row line such that only one or more of those capacitor elements having a terminal connected to the selected row line are biased into a double-valued portion of their hysteresis loops, the others being in a single-valued portion, and for applying a second voltage singal to the selected row line within the time duration of and superimposed on the first voltage pulse, whereby the electrical current response to said second voltage signal of at least one of the capacitors having a terminal connected to the selected row line is indicative of the respective memory state of this capaccitor.
Claim 3
Dependent Claim
16 words
Apparatus according to claim 1 in which the second voltage signal is a rectangular voltage pulse.
Claim 4
Dependent Claim
22 words
Apparatus according to claim 1 in which all memory cells have a semiconductor-insulator1-insulator2-metal layered structure integrated in a single semiconductor wafer substrate.
Claim 5
Dependent Claim
22 words
Apparatus according to claim 1 in which all memory cells have a metal-insulator-semiconductor layered structure integrated in a single semiconductor wafer substrate.
Claim 6
Dependent Claim
11 words
Apparatus according to claim 4 in which the semiconductor is silicon.
Claim 7
Dependent Claim
18 words
Apparatus according to claim 4 in which the insulator includes at least two layers of different insulator materials.
Claim 8
Independent Claim
117 words
The method of addressing a rectangular array of substantially identical, crosspoint connected, hysteresis loop type memory capacitor cells which comprises the step of applying a first voltage pulse to a conductive line along which a selected cell is connected, said first pulse being sufficient to bias at least the selected cell into a double-valued portion of its hysteresis loop while all cells along other lines are biased in a single-valued portion of their respective hysteresis loop characteristics, and the step of applying a second voltage signal within the time duration of and superimposed upon the first voltage pulse, whereby the electrical current response to said second signal of the selected cell is indicative of its memory state.
Claim 9
Independent Claim
117 words
The method of addressing a rectangular array of substantially identical, crosspoint connected, hysteresis loop type memory capacitor cells which comprises the step of applying a first voltage pulse to a conductive line along which a selected cell is connected, said first pulse being sufficient to bias at least the selected cell into a double-valued portion of its hysteresis loop while all cells along other lines are biased in a single-valued portion of their respective hysteresis loop characteristics, and the step of applying a second voltage signal within the time duration of and superimposed upon the first voltage pulse, whereby the electrical current response to said second signal of the selected cell is indicative of its memory state.
Claim 10
Dependent Claim
16 words
The method recited in claim 7 in which the first signal is a rectangular voltage pulse.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-01-06 | 1978-07-08 | 1979-01-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-01-06 | 1982-07-08 | 1983-01-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-01-06 | 1986-07-08 | 1987-01-07 | $7700.00 | Window Closed / Lapsed |