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US4069426A
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Complementary MOS logic circuit
Assignee: Toshiba Corp
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Filing: 1976-10-05
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Granted: 1978-01-17
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Expires: 1996-10-05
Abstract
Abstract A complementary MOS logic circuit for obtaining second logic signals corresponding to a large number of logic combinations derived from a group of first logic signals, wherein a plurality of series circuits each formed of a plurality of series-connected first channel type IG-FET's and a plurality of series circuits each formed of a plurality of series-connected second channel type IG-FET's are jointly connected to the output terminal of said complementary MOS type logic circuit; the gates of the first and second channel type IG-FET's are supplied with first logic signals and those complementary thereto to specify a desired block circuit consisting of the component series circuits formed of the first and second channel type IG-FET's; and a second logic signal is conducted to the output terminal through the specified block circuit.
Inventors
- 👤 Masataka Hirasawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 11:09
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/1733
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
148 words
A complementary MOS logic circuit for obtaining second logic signals corresponding to the state of logic combinations specified by N first logic signals wherein N is greater than 2 which logic circuit comprises a plurality of block series circuits each consisting of a first component series circuit formed of series connected first channel type IG-FET's and a second component series circuit formed of series connected second channel type IG-FET's arranged complementary to said first channel type IG-FET's and having a common output terminal connected to all the component series circuits; said N first logic signals or those complementary thereto being selectively supplied to the gates of the first and second channel type IG-FET's to selectively conduct the second logic signals to the output terminal of the complementary MOS logic circuit through a predetermined component series circuit in response to said N first logic signals or those complementary thereto.
Claim 2
Dependent Claim
148 words
A complementary MOS logic circuit for obtaining second logic signals corresponding to the state of logic combinations specified by N first logic signals wherein N is greater than 2 which logic circuit comprises a plurality of block series circuits each consisting of a first component series circuit formed of series connected first channel type IG-FET's and a second component series circuit formed of series connected second channel type IG-FET's arranged complementary to said first channel type IG-FET's and having a common output terminal connected to all the component series circuits; said N first logic signals or those complementary thereto being selectively supplied to the gates of the first and second channel type IG-FET's to selectively conduct the second logic signals to the output terminal of the complementary MOS logic circuit through a predetermined component series circuit in response to said N first logic signals or those complementary thereto.
Claim 3
Dependent Claim
140 words
A complementary MOS logic circuit according to claim 1, wherein the first component series circuit of each block constituted by the first channel type IG-FET's and the second component series circuit of said block constituted by the second channel type IG-FET's are connected together in series to allow activation of a predetermined component series circuit for each state of logic combinations of said N first logic signals or those complementary thereto; the component series circuits of all the blocks are disposed between two power supply lines; and the gate of at least one of the first channel type IG-FET's constituting a component series circuit or the gate of at least one of the second channel type IG-FET's of each block constituting a counterpart component series circuit is supplied with any of the second logic signals or a signal complementary thereto.
Claim 4
Dependent Claim
97 words
A complementary MOS logic circuit according to claim 1, where a first source electrode of the first channel type IG-FET on that end of the first component series circuit of each block which is disposed opposite to the output point of said first component series circuit and a second source electrode of the second channel type IG-FET on that end of the second component circuit of said block which is disposed opposite to the output point of said second component series circuit are supplied with a signal complementary to the second logic signal corresponding to each block.
Claim 5
Dependent Claim
61 words
A complementary MOS logic circuit according to claim 1, wherein when the second logic signals include complementary ones, one of said complementary signals is supplied to a source electrode constituting the end portion of each block series circuit and also to a gate electrode constituting the other block series circuit corresponding to a signal complementary to said one second logic signal.
Claim 6
Dependent Claim
65 words
A complementary MOS logic circuit according to claim 1, wherein the block series circuits are arranged between two power source lines and the first and second component series are simplified by replacing two IG-FET's of the same channel type having the sources or the drains connected to the same power source line and the gates supplied with the same input signals by a single IG-FET.
Claim 7
Dependent Claim
49 words
A complementary MOS logic circuit according to claim 5, wherein the number IG-FET's connected to the same power source line is maximized and the IG-FET's connected to the output terminal is minimized, and each block series circuit comprises the same number of the first and second channel type IG-FET's.
Claim 8
Dependent Claim
61 words
A complementary MOS logic circuit according to claim 1, wherein two IG-FET's of the same channel type having gates supplied with the second logic signals are replaced by a single IG-FET where two second logic signals are common to each other and the component series circuits comprising said two IG-FET's are connected by using the single IG-FET replacing said two IG-FET's.
Claim 9
Dependent Claim
56 words
A complementary MOS logic circuit according to claim 1, wherein some of the second logic signals are constantly set at a predetermined logic level, and the IG-FET of each component series circuit having a gate supplied with said constantly set second logic signals of predetermined logic level is omitted in correspondence to the predetermined logic level.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-01-16 | 1981-07-18 | 1982-01-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-01-16 | 1985-07-18 | 1986-01-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-01-16 | 1989-07-18 | 1990-01-17 | $7700.00 | Window Closed / Lapsed |