US3720841A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Logical circuit arrangement
Assignee: Toshiba Corp
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Filing: 1971-12-28
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Granted: 1973-03-13
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Expires: 1991-12-28
Abstract
Abstract A logical circuit arrangement is comprised by a switching circuit including a first logic unit constituted by insulated gate field effect transistors of one conductivity type channel and a second logic unit constituted by insulated gate field effect transistors of the other conductivity type channel; a shift register applied with the output switching circuit and including a plurality of bit elements, each constituted by first and second cascade connected complementary inverters which are composed of insulated gate field effect transistors of the complementary conductivity type channel; a complementary buffer circuit connected to the output from the buffer circuit to the first and second logic units; and a circuit for applying a logical input data signal, a control pulse and a complement signal of the control signal to the gate electrodes of the insulated gate field effect transistors of the switching circuit respectively for selectively switching the polarity of the logical output of the first and second logic units to supply said shift register with said input data signal or an output signal of said buffer circuit in accordance with said control pulse and the complemental pulse of the control pulse.
Inventors
- 👤 Y Suzuki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 05:33
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/096; H03K19/0963; G; G11; G11C; G11C19/00; G11C19/18; G11C19/182; G11C19/184
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
387 words
A logical circuit arrangement comprising, a. a switching circuit including a first logic unit having first and second logic elements which are connected in parallel, each one of said first and second logic elements including two serially connected insulated gate field effect transistors of one conductivity type channel, a second logic unit having third and fourth logic elements which are connected in parallel, each one of said third and fourth logic elements including two serially connected insulated gate field effect transistors of the other conductivity type channel, said first and second logic units being connected in series across source terminals, and an output terminal of said switching circuit connected to the node between said first and second logic units; b. a shift register including a plurality of bit elements, each including cascade connected first and second complementary inverters, each one of said complementary inverters having a pair of insulated gate field effect transistors of the one and the other conductivity type channels, and insulated gate field effect transistors of the one and the other conductivity type channels respectively connected in series with said insulated gate field effect transistors of the one and the other conductivity type channels which constitute the complementary inverters, said shift register operating to successively shift said output from said switching circuit in accordance with first and second clock pulses having a predetermined phase difference and are supplied respectively to said first and second complementary inverters; c. a buffer circuit connected to the output terminal of said shift register and including complementary insulated gate field effect transistors; d. means to feedback the output from said buffer circuit to the gate electrodes of the insulated gate field effect transistors of said one conductivity type channel of said second and fourth logic elements of said first and second logic units; and e. a circuit for applying a logical input data signal, a control pulse and a complementary pulse of said control pulse upon the gate electrodes of said insulated gate field effect transistor of said switching circuit respectively for selectively switching the level of the logical output from said first and second logic units to supply said shift register with said input data signal or an output signal of said buffer circuit in accordance with said control pulse and said complementary pulse of said control pulse.
Claim 2
Dependent Claim
387 words
A logical circuit arrangement comprising, a. a switching circuit including a first logic unit having first and second logic elements which are connected in parallel, each one of said first and second logic elements including two serially connected insulated gate field effect transistors of one conductivity type channel, a second logic unit having third and fourth logic elements which are connected in parallel, each one of said third and fourth logic elements including two serially connected insulated gate field effect transistors of the other conductivity type channel, said first and second logic units being connected in series across source terminals, and an output terminal of said switching circuit connected to the node between said first and second logic units; b. a shift register including a plurality of bit elements, each including cascade connected first and second complementary inverters, each one of said complementary inverters having a pair of insulated gate field effect transistors of the one and the other conductivity type channels, and insulated gate field effect transistors of the one and the other conductivity type channels respectively connected in series with said insulated gate field effect transistors of the one and the other conductivity type channels which constitute the complementary inverters, said shift register operating to successively shift said output from said switching circuit in accordance with first and second clock pulses having a predetermined phase difference and are supplied respectively to said first and second complementary inverters; c. a buffer circuit connected to the output terminal of said shift register and including complementary insulated gate field effect transistors; d. means to feedback the output from said buffer circuit to the gate electrodes of the insulated gate field effect transistors of said one conductivity type channel of said second and fourth logic elements of said first and second logic units; and e. a circuit for applying a logical input data signal, a control pulse and a complementary pulse of said control pulse upon the gate electrodes of said insulated gate field effect transistor of said switching circuit respectively for selectively switching the level of the logical output from said first and second logic units to supply said shift register with said input data signal or an output signal of said buffer circuit in accordance with said control pulse and said complementary pulse of said control pulse.
Claim 3
Dependent Claim
387 words
A logical circuit arrangement comprising, a. a switching circuit including a first logic unit having first and second logic elements which are connected in parallel, each one of said first and second logic elements including two serially connected insulated gate field effect transistors of one conductivity type channel, a second logic unit having third and fourth logic elements which are connected in parallel, each one of said third and fourth logic elements including two serially connected insulated gate field effect transistors of the other conductivity type channel, said first and second logic units being connected in series across source terminals, and an output terminal of said switching circuit connected to the node between said first and second logic units; b. a shift register including a plurality of bit elements, each including cascade connected first and second complementary inverters, each one of said complementary inverters having a pair of insulated gate field effect transistors of the one and the other conductivity type channels, and insulated gate field effect transistors of the one and the other conductivity type channels respectively connected in series with said insulated gate field effect transistors of the one and the other conductivity type channels which constitute the complementary inverters, said shift register operating to successively shift said output from said switching circuit in accordance with first and second clock pulses having a predetermined phase difference and are supplied respectively to said first and second complementary inverters; c. a buffer circuit connected to the output terminal of said shift register and including complementary insulated gate field effect transistors; d. means to feedback the output from said buffer circuit to the gate electrodes of the insulated gate field effect transistors of said one conductivity type channel of said second and fourth logic elements of said first and second logic units; and e. a circuit for applying a logical input data signal, a control pulse and a complementary pulse of said control pulse upon the gate electrodes of said insulated gate field effect transistor of said switching circuit respectively for selectively switching the level of the logical output from said first and second logic units to supply said shift register with said input data signal or an output signal of said buffer circuit in accordance with said control pulse and said complementary pulse of said control pulse.
Claim 4
Dependent Claim
387 words
A logical circuit arrangement comprising, a. a switching circuit including a first logic unit having first and second logic elements which are connected in parallel, each one of said first and second logic elements including two serially connected insulated gate field effect transistors of one conductivity type channel, a second logic unit having third and fourth logic elements which are connected in parallel, each one of said third and fourth logic elements including two serially connected insulated gate field effect transistors of the other conductivity type channel, said first and second logic units being connected in series across source terminals, and an output terminal of said switching circuit connected to the node between said first and second logic units; b. a shift register including a plurality of bit elements, each including cascade connected first and second complementary inverters, each one of said complementary inverters having a pair of insulated gate field effect transistors of the one and the other conductivity type channels, and insulated gate field effect transistors of the one and the other conductivity type channels respectively connected in series with said insulated gate field effect transistors of the one and the other conductivity type channels which constitute the complementary inverters, said shift register operating to successively shift said output from said switching circuit in accordance with first and second clock pulses having a predetermined phase difference and are supplied respectively to said first and second complementary inverters; c. a buffer circuit connected to the output terminal of said shift register and including complementary insulated gate field effect transistors; d. means to feedback the output from said buffer circuit to the gate electrodes of the insulated gate field effect transistors of said one conductivity type channel of said second and fourth logic elements of said first and second logic units; and e. a circuit for applying a logical input data signal, a control pulse and a complementary pulse of said control pulse upon the gate electrodes of said insulated gate field effect transistor of said switching circuit respectively for selectively switching the level of the logical output from said first and second logic units to supply said shift register with said input data signal or an output signal of said buffer circuit in accordance with said control pulse and said complementary pulse of said control pulse.
Claim 5
Dependent Claim
143 words
The logical circuit arrangement according to claim 1 wherein said switching circuit includes first and second insulated gate field effect transistors having the same conductivity type channels as said insulated gate field effect transistors of said first and second logic circuit, said first and second insulated gate field effect transistors being connected between said first and second logic units and a source terminal and impressed with sAid first clock pulse upon the gate electrodes thereof, and wherein the first bit element of said shift register comprises a second complementary inverter connected to receive directly the output from said switching circuit and insulated gate field effect transistors of the one and the other conductivity type channels and are respectively connected in series with said insulated gate field effect transistors of the one and the other conductivity type channels which constitute said second complementary inverter.
Claim 6
Dependent Claim
34 words
The logical circuit arrangement according to claim 1 wherein said buffer circuit comprises a single stage complementary inverter constituted by a pair of insulated gate field effect transistors of the opposite conductivity type channels.
References Cited (Backward Citations)
US3431433A
Cited
US3609392A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-03-12 | 1976-09-11 | 1977-03-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-03-12 | 1980-09-11 | 1981-03-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-03-12 | 1984-09-11 | 1985-03-13 | $7700.00 | Window Closed / Lapsed |