Programmable switching array

Claim 1

Apparatus for generating signals representing desired sequential logical functions Zj, j 0, 1, 2 . . . , (N1-1) of one or more input logic variables Xi, i 0, 1, . . . , (N2-1) comprising a plurality of substantially identical logic modules arranged in a rectangular array having a plurality of ordered rows and a plurality of N2 ordered columns, each of said logic modules comprising a plurality of input terminals, at least one output terminal, and circuit means including delay means for generating at said output terminal, signals representing a fixed sequential function of logic variables represented by signals applied at said input terminals, means for applying signals representing one or more of said input logic variables to selected modules in the first row of said array, said means for applying comprising means for applying signals representing the ith input logic variable to an input terminal of the module in the first row of the ith column, said apparatus further comprising means for extending the application of said signals representing the ith one of said variable to an input terminal of each module in said ith column, connecting means interconnecting selected ones of said modules Appearing in a given column, other than the last, to modules appearing in the immediately succeeding column, said connecting means extending from a given module in said given column only to selected ones of the set of modules in said succeeding column which set includes the module in the same row as said given module and those in consecutive adjacent rows, said circuit means in each of said logic modules comprising means for generating at time t+1 the fixed function, fij0 Xi'' + fij1 Xi, where Xi is the input variable X applied to the ith column of the array, Xi'' is the complement of Xi, and fij0 and fij1 are the logical functions of one or more of the input variables other than X0 each applied at time t, and output means connected to selected ones of the modules in the last column of said array, said output means comprising N1 ordered output leads each connected to an output terminal of a respective one of said selected modules in the last column of said array, each of said output leads corresponding to one of said desired logical functions, and wherein at least one of said output leads is connected to an input terminal in each of the modules in the first row of said array.