Universal logic circuitry having modules with minimum input-output connections and minimum logic gates

Claim 2

A universal logic circuit for providing the function for at least three variables x1, x2 and x3 comprising input means including at least one group of paths C1, C1 for providing x1, x1 inputs, a second group of paths C2, C2 for providing x2, x2 inputs, a third group of paths for providing four separate inputs representing the residue functions f(0,0,x3) f(0,1,x3) f(1,0,x3) and f(1,1,x3) of a function f(x1, x2, x3) of three variables x1, x2, and x3 expanded as functions of x3 only; at least four logic gates comprising one gate connected to the paths for the x1, x2 and f(0,0,x3) inputs, a second gate connected to the paths for the x1, x2, f(0,1,x3) inputs, a third gate connected to the paths for the x1, x2, f(1,0,x3) inputs, and a fourth gate connected to the paths for the x1, x2, f(1,1,x3) inputs, and output means connected to combine the outputs of said four gates.

Claim 3

A universal logic circuit as set forth in claim 1 in which said input means includes six input terminals for said logic circuit, comprising a first input terminal for input x1, a second input terminal for x2, and four separate terminals for said four residue functions, and inverter means connected to said C1, C2 input terminals to provide said x1, x2 signals for said C1, C2 paths.

Claim 4

A universal logic circuit as set forth in claim 1 in which each of said logic gates includes a diode for each input thereto, and said output means including a plurality of semiconductor devices, each device respectively connected to the output of the diodes in an associated gate.

Claim 5

A universal logic circuit as set forth in claim 1 in which the number of variables is n 3, and the number of input pins p is 2n 1+n-1 6.

Claim 6

A universal logic circuit for providing the function for at least four variables x1, x2, x3 and x4 comprising input means including at least one group of input paths C1, C1 for providing x1, x1 inputs, a second group of input paths C2, C2 for providing x2, x2 inputs, a third group of input paths C3, C3 for providing x3, x3 inputs, and a fourth group oF paths for each of the residue functions of f(x1 x2 x3 x4) expanded as functions of x4 only, at least eight logic gates comprising one gate connected to input paths for x1, x2, x3 and f(0,0,0,x4), a second gate connected to the input paths for x1, x2, x3 and f(0,0,1,x4), a third gate connected to the input paths for x1, x2, x3 and f(0,1, 0,x4), a fourth gate connected to the input paths for x1, x2, x3 and f(0,1,1,x4), a fifth gate connected to the input paths for x1, x2, x3 and f(1,0,0,x4), a sixth gate connected to the input paths for x1, x2, x3 and f(1,0,1,x4), a seventh gate connected to the input paths for x1, x2, x3 and f(1,1,0,x4), an eighth gate connected to the input paths for x1, x2, x3 and f(1,1,1,x4), and output means for combining the function outputs provided by said eight gates.

Claim 7

A universal logic circuit for providing the function for at least four variables x1, x2, x3 and x4 comprising input means including at least one group of input paths C1, C1 for providing x1, x1 inputs, a second group of input paths C2, C2 for providing x2, x2 inputs, a third group of input paths C3, C3 for providing x3, x3 inputs, and a fourth group oF paths for each of the residue functions of f(x1 x2 x3 x4) expanded as functions of x4 only, at least eight logic gates comprising one gate connected to input paths for x1, x2, x3 and f(0,0,0,x4), a second gate connected to the input paths for x1, x2, x3 and f(0,0,1,x4), a third gate connected to the input paths for x1, x2, x3 and f(0,1, 0,x4), a fourth gate connected to the input paths for x1, x2, x3 and f(0,1,1,x4), a fifth gate connected to the input paths for x1, x2, x3 and f(1,0,0,x4), a sixth gate connected to the input paths for x1, x2, x3 and f(1,0,1,x4), a seventh gate connected to the input paths for x1, x2, x3 and f(1,1,0,x4), an eighth gate connected to the input paths for x1, x2, x3 and f(1,1,1,x4), and output means for combining the function outputs provided by said eight gates.

Claim 8

A universal logic circuit as set forth in claim 5 in which each of said eight gates is connected to only the paths for providing said x2,x3,x2,x3 inputs and the indicated residue functions, and which includes a first additional gate means connected to the outputs of a first plurality of said eight gates and said x1 input, and a second additional gate means connected to the outputs of the remaining one of said eight gates and said x1 input, and in which the output of said first and second additional gate means is connected to said output means.

Claim 9

A universal logic circuit for providing the function for a plurality of n variables x1, x2,...,xn comprising input means including at least one group of paths C1, C1 for providing x1, x1 inputs, a second group of paths C2, C2 for providing x2, x2 inputs, a third group of paths for providing at least four separate inputs representing the residue functions f(0,0,...,xn), f(0,1,...,xn), f(1,0,...,xn), and f(1,1,...,xn) of a function f(x1,x2,...,xn) of n variables x1, x2,...,xn expanded as a function of xn only; at least four logic gates comprising one gate connected at least to the paths for the x1, x2 and f(0,0, ...,xn) inputs, a second gate connected at least to the paths for the x1,x2, f(0,1,...,xn) inputs a third gate connected to at least the paths for the x1, x2, f(1,0,...,xn) inputs, and a fourth gate connected to at least the paths for the x1, x2, f(1, 1,...,xn) inputs, and a fourth gate connected to at least the paths for the x1, x2, x1,x2, f(1,1,...,xn) inputs, and output means connected to combine the outputs of said gates.

Claim 10

A universal logic circuit for providing the function for a plurality of n variables x1, x2,...,xn comprising input means including at least one group of paths C1, C1 for providing x1, x1 inputs, a second group of paths C2, C2 for providing x2, x2 inputs, a third group of paths for providing at least four separate inputs representing the residue functions f(0,0,...,xn), f(0,1,...,xn), f(1,0,...,xn), and f(1,1,...,xn) of a function f(x1,x2,...,xn) of n variables x1, x2,...,xn expanded as a function of xn only; at least four logic gates comprising one gate connected at least to the paths for the x1, x2 and f(0,0, ...,xn) inputs, a second gate connected at least to the paths for the x1,x2, f(0,1,...,xn) inputs a third gate connected to at least the paths for the x1, x2, f(1,0,...,xn) inputs, and a fourth gate connected to at least the paths for the x1, x2, f(1, 1,...,xn) inputs, and a fourth gate connected to at least the paths for the x1, x2, x1,x2, f(1,1,...,xn) inputs, and output means connected to combine the outputs of said gates.

Claim 11

A Universal logic circuit as set forth in claim 7 in which the number of variables is n and the number of input pins p is 2n 1+n-1.

Claim 12

In a circuit as set forth in claim 7 in which the number of inputs to each gate is limited to four and in which the number of levels l is

Claim 13

In a circuit as set forth in claim 7 in which the number of inputs to each gate is limited to four, and which has q gates when