Clocked dynamic inverter

Claim 1

A dynamic logic circuit having input and output terminals and comprising: an input data signal source; first voltage-responsive switching means having first and second terminals with a variable resistive path defined therebetween, and an actuable control terminal connected to said data source, said terminal, in response to different data signal levels, selectively switching said path from a first state exhibiting a relatively high value of resistance to a second state exhibiting a relatively low value of resistance, said first terminal being connected to the output terminal, said second terminal being connected to a circuit ground return, and said control terminal being connected to the input terminal; a field-effect load transistor having source, drain and gate electrodes, said drain electrode being adapted for biasing at a predetermined voltage level and said source electrode being connected to the first terminal of said first switching means and to the output terminal; a first clock pulse source for producing a first train of pulses at a first predetermined voltage level and repetition rate; a bias voltage source; second voltage-responsive switching means connected between said first clock source and said gate electrode of said load transistor, said second switching means, in response to each first clock source pulse applied thereto, establishing a relatively low resistance path therethrough, and supplying from said bias voltage source a periodic turnON bias voltage level on said gate electrode of said load transistor; capacitor means connected between said source electrode and said gate electrode of said load transistor, said capacitor means feeding back to the gate electrode of said load transistor at least a portion of the output signal established during each successive period in which a pulse from said first clock source occurs while said first switching means is in said first high resistance state, said feedback voltage being sufficient, when combined with the voltage supplied periodically by said second switching means in response to each successive pulse from said first clock source applied thereto, to produce a substantial overdriving gate-to-source electrode voltage differential so as to produce a rapid output signal transition in the direction toward and reaching the level of the voltage applied to the drain electrode of said load transistor; a second clock source for producing a second train of pulses in a sequential manner with said first train; third voltage-responsive switching means having first and second terminals with a variable resistive path defined therebetween, and an actuable control terminal for selectively switching said path from a first state exhibiting a relatively high value of resistance to a second state exhibiting a relatively low value of resistance, said first tErminal being connected to said gate electrode of said load transistor, said second terminal being connected to a predetermined ground return potential, and said control terminal being connected to said second clock source, the repetition rate of said pulses from said first and second clock sources being further correlated with the rate at which input data signals are applied to said input terminal, and a predetermined value of storage capacitance coupled to said gate electrode of said load transistor said value of storage capacitance being much smaller than the capacitance of said feedback capacitor means, said storage capacitance being periodically charged by pulsed turn-ON bias voltage applied thereto through said second switching means interconnection and, thereafter, temporarily providing a transient bias voltage on said gate electrode after each pulsed bias voltage from said first clock source has terminated.