Three-phase clock signal generator using two-phase clock signals

Claim 2

A three-phase clock signal generator gated by two-phase clock signals comprising a multiple-phase clocking scheme, said generator having an output and comprising, a first field effect transistor means connected between said output and a first two-phase clocking signal for driving said output to a first logical level during a first phase of said first two-phase clock signal, a second field effect transistor means connected between said output and a voltage level for maintaining the output at said first logical level during second and third consecutive phases of said two-phase clock signals, said second field effect transistor means having a gate electrode, a storage capacitor for supplying a drive voltage to said gate electrode during said second and third consecutive phases, said second field effect transistor means further including circuit means responsive to a second two-phase clock signal for charging said storage capacitor prior to said first phase, a third field effect transistor means including a gate electrode responsive to a third two-phase clock signal for driving said output to a second logical level during a fourth consecutive phase of said two-phase clock signals, said first recited phase following said fourth recited phase, said output connected at a common point between said first, second and third field effect transistor means.

Claim 3

A three-phase clock signal generator gated by two-phase clock signals comprising a multiple-phase clocking scheme, said generator having an output and comprising, a first field effect transistor means for driving said output to a first logical level during a first phase of said two-phase clock signals, said first field effect transistor means is connected between said output and a first two-phase clock signal, said first field effect transistor means including feedback capacitor means connected between the output and the gate electrode of said first field effect transistor means for driving said output to the signal level of a first two-phase clock signal during said first phase, a second field effect transistor means for maintaining the output at said first logical level during second and third consecutive phases of said two-phase clock signals, said second field effect transistor means is connected between said output and a voltage level and includes feedback capacitor means connected between the output and gate electrode of said second field effect transistor means for overcoming the threshold losses through said second field effect transistor means, a third field effect transistor means for driving said output to a second logical level during a fourth consecutive phase of said two-phase clock signals, said first recited phase following said fourth recited phase, said third field effect transistor means is connected between said output and a second two-phase clock signal, said third field effect transistor means having its gate electrode connected to a third two-phase clock signal, said second two-phase clock signal and third two-phase clock signal having an overlapping phase whereby during said fourth consecutive phase said third field effect transistor means drives said output to the signal level of said second two-phase clock signal, said signal level being approximately equal to said second logical level during said fourth consecutive phase.

Claim 4

A three-phase clock signal generator gated by two-phase clock signals comprising a multiple-phase clocking scheme, said generator having an output and comprising, a first field effect transistor means for driving said output to a first logical level during a first phase of said two-phase clock signals, said first field effect transistor means is connected between said output and a first two-phase clock signal, said first field effect transistor means including feedback capacitor means connected between the output and the gate electrode of said first field effect transistor means for driving said output to the signal level of a first two-phase clock signal during said first phase, a second field effect transistor means for maintaining the output at said first logical level during second and third consecutive phases of said two-phase clock signals, said second field effect transistor means is connected between said output and a voltage level and includes feedback capacitor means connected between the output and gate electrode of said second field effect transistor means for overcoming the threshold losses through said second field effect transistor means, a third field effect transistor means for driving said output to a second logical level during a fourth consecutive phase of said two-phase clock signals, said first recited phase following said fourth recited phase, said third field effect transistor means is connected between said output and a second two-phase clock signal, said third field effect transistor means having its gate electrode connected to a third two-phase clock signal, said second two-phase clock signal and third two-phase clock signal having an overlapping phase whereby during said fourth consecutive phase said third field effect transistor means drives said output to the signal level of said second two-phase clock signal, said signal level being approximately equal to said second logical level during said fourth consecutive phase.

Claim 5

The generator recited in claim 2 and further including a fourth field effect transistor means connected between the gate electrode of said first field effect transistor means and a fourth two-phase clock signal, said fourth field effect transistor means having its gate electrode connected to said first two-phase clock signal, said first and fourth two-phase clock signals having one overlapping phase whereby said first recited field effect transistor means becomes conductive during said first recited phase for driving said output to the signal level of said first two-phase clock signal, said signal level being equal to said first recited logical level.

Claim 6

The generator recited in claim 3 wherein said three-phase clock signal generator includes fifth and sixth field effect transistor means individually connected between the gate electrodes of said first and second field effect transistor means respectively and a voltage level, said fifth and sixth field effect transistor means having their gate electrodes connected to said fourth two-phase clock signal for applying approximately said voltage level to the gate electrodes of said first and second field effect transistor means during said fourth recited phase whereby said feedback capacitors are precharged prior to receiving a feedback from said output during said first phase.

Claim 7

The generator recited in claim 4 wherein said first, second, third and fourth recited two-phase clock signals are phi 3 4, phi 4 1, phi 1 2, and phi 2 3, respectively for generating a three-phase clock signal phi 3 4 1, and said first, second, third, and fourth two-phase clock signals are phi 4 1, phi 1 2, phi 2 3, and phi 3 4, for generating a three-phase clock signal phi 4 1 2, and said first, second, third, and fourth two-phase clock signals are phi 1 2, phi 2 3, phi 3 4, and phi 4 1, for generating the three-phase clock signal phi 1 2 3, and said first, second, third and fourth two-phase clock signals are phi 2 3, phi 3 4, phi 4 1, and phi 1 2, for generating a three-phase clock signal phi 2 3 4.