Field effect transistor single-phase clock signal generator

Claim 2

A single-phase clock signal field effect generator comprising, a first field effect transistor having source, drain, and gate electrodes, said source electrode connected to an output, a capacitor connected between said source electrode and said gate electrode, a second field effect transistor having a source, drain, and gate electrode, said source electrode being connected to the gate electrode of said first field effect transistor, a third field effect transistor having a source, drain, and gate electrode, said drain electrode connected to said output, a fourth field effect transistor having a source, drain, and gate electrode, said source electrode connected to the gate electrode of said third field effect transistor, a fifth field effect transistor having a source, drain and gate electrode, said source electrode connected to the gate electrode of said third field effect transistor, and to the source electrode of said fourth field effect transistor.

Claim 3

The generator recited in claim 1 further including a sixth field effect transistor having a source, drain, and gate electrode, said drain electrode being connected to the gate electrode of said first field effect transistor.

Claim 4

A single-phase clock signal generator using double- and single-phase clock signals of a multiphase clock cycle, said generator comprising, a first field effect transistor driver connected between a voltage level and an output and having a gate electrode, said voltage level being provided at the output at least during the phase interval of the single-phase clock signal being generated, a capacitor connected between the output and the gate electrode for feeding back the output voltage to the gate electrode during the single phase of the clock signal being generated, a second field effect transistor connected to the gate electrode for precharging the capacitor prior to the single phase of the clock signal being generated, a third field effect transistor connected between the output and a referenced voltage level, said third field effect transistor having a gate electrode connected to a voltage level transistor having a gate electrode connected to a voltage level for holding said field effect transistor on until the single-phase of the generated clock signal and said gate electrode being connected to a different voltage level for holding said field effect transistor off during the phase of the clock signal being generated, the application of said voltage levels to said gate electrode being controlled by a different single-phase clock signal and by at least one double-phase clock signal, a fourth field effect transistor connected between the gate electrode of said third field effect transistor and said different single-phase clock signal, said fourth field effect transistor being gated by a double-phase clock signal with the first phase of said double-phase clock signal being equal to the phase of said different single-phase clock signal whereby during the first phase of said double-phase clock signal said diffErent single-phase clock signal is applied to the gate electrode of said third field effect transistor for holding said third field effect transistor on, said single phase immediately preceding the single phase of the single-phase clock being generated, said different single-phase clock signal being false during the second phase of said double-phase clock signal, said fourth field effect transistor being on during said second phase for applying said false signal level to the gate electrode of said third field effect transistor whereby said third field effect transistor is turned off, said third field effect transistor being off at the beginning of the phase of the single-phase clock signal being generated for enabling a voltage level to appear at the output, the voltage level appearing at said output being fed back across said capacitor to the gate electrode of said first field effect transistor for boosting the gate electrode voltage of said first field effect transistor, said boosted gate electrode voltage enhancing the conduction of said first field effect transistor for substantially overcoming the inherent threshold voltage loss across said first field effect transistor whereby the output is driven to approximately said first recited voltage level without a threshold loss.

Claim 5

A single-phase clock signal generator using double- and single-phase clock signals of a multiphase clock cycle, said generator comprising, a first field effect transistor driver connected between a voltage level and an output and having a gate electrode, said voltage level being provided at the output at least during the phase interval of the single-phase clock signal being generated, a capacitor connected between the output and the gate electrode for feeding back the output voltage to the gate electrode during the single phase of the clock signal being generated, a second field effect transistor connected to the gate electrode for precharging the capacitor prior to the single phase of the clock signal being generated, a third field effect transistor connected between the output and a referenced voltage level, said third field effect transistor having a gate electrode connected to a voltage level transistor having a gate electrode connected to a voltage level for holding said field effect transistor on until the single-phase of the generated clock signal and said gate electrode being connected to a different voltage level for holding said field effect transistor off during the phase of the clock signal being generated, the application of said voltage levels to said gate electrode being controlled by a different single-phase clock signal and by at least one double-phase clock signal, a fourth field effect transistor connected between the gate electrode of said third field effect transistor and said different single-phase clock signal, said fourth field effect transistor being gated by a double-phase clock signal with the first phase of said double-phase clock signal being equal to the phase of said different single-phase clock signal whereby during the first phase of said double-phase clock signal said diffErent single-phase clock signal is applied to the gate electrode of said third field effect transistor for holding said third field effect transistor on, said single phase immediately preceding the single phase of the single-phase clock being generated, said different single-phase clock signal being false during the second phase of said double-phase clock signal, said fourth field effect transistor being on during said second phase for applying said false signal level to the gate electrode of said third field effect transistor whereby said third field effect transistor is turned off, said third field effect transistor being off at the beginning of the phase of the single-phase clock signal being generated for enabling a voltage level to appear at the output, the voltage level appearing at said output being fed back across said capacitor to the gate electrode of said first field effect transistor for boosting the gate electrode voltage of said first field effect transistor, said boosted gate electrode voltage enhancing the conduction of said first field effect transistor for substantially overcoming the inherent threshold voltage loss across said first field effect transistor whereby the output is driven to approximately said first recited voltage level without a threshold loss.

Claim 6

The generator recited in claim 3 wherein said second field effect transistor is clocked by said different single-phase clock signal, the phase of said different single-phase clock signal immediately preceding the phase of the generated single-phase clock signal whereby said precharging occurs during the phase of said multiphase clock cycle immediately preceding the phase of the generated clock signal, said voltage level being provided by said double-phase clock signal, the later-occurring phase of said double-phase clock signal comprising the phase during which said single-phase clock signal is generated, a fifth field effect transistor connected between the gate electrode of said first field effect transistor and said reference voltage level, said fifth field effect transistor being gated by a double-phase clock signal having a distinct phase relationship relative to said first recited double-phase clock signal for holding the gate electrode of said first field effect transistor at said reference voltage level until the phase immediately preceding the phase of the generated single-phase clock signal.

Claim 7

The generator recited in claim 3 wherein a voltage level is applied to the gate electrode of said third field effect transistor through a field effect transistor connected in series between said voltage level and said gate electrode, said voltage being applied to said gate electrode during the phase times of said multiphase clock cycle immediately preceding the phase times of said first recited double-phase clock signal, said voltage level being provided by a double-phase clock signal which precedes in phase said first-recited double-phase clock signal, said series-connected field effect transistor having its gate electrode connected to said second-recited double-phase clock signal.