Multiple phase clock generator circuit

Claim 2

A multiple phase clock signal generator comprising, an RC oscillator circuit generating multiple and phase related signals, a multi-bit shift register in which outputs from certain bit positions of the shift register are inverted and fed back as inputs to other bit positions of the shift register, said shift register being gated by the signals generated by said RC oscillator circuit, and output logic gates generating multiphase clock signals in response to outputs from said shift register and in response to certain multiphase clock signals fed back from the outputs of said logic gates for providing a synchronized relationship between the multiphase clock signals being generated.

Claim 3

The multiphase clock signal generator recited in claim 1 wherein said multi-bit shift register has a plurality of bit positions determined as a function of the number of phases of said multiphase clock signals.

Claim 4

The multiphase clock signal generator recited in claim 2 wherein the RC time constant of said RC oscillator is selected for generating said signals with a cycle equivalent to one phase of said multiphase clock signals.

Claim 5

The multiphase clock signal generator recited in claim 3 wherein said RC oscillator circuit, said multi-bit shift register, and said output logic gates, are implemented by field effect transistors.

Claim 6

The multiphase clock signal generator recited in claim 1 wherein said RC oscillator circuit comprises first and second inverter circuits responsive to the charge and discharge voltage levels of the RC circuit for providing a first square wave output signal from said RC oscillator circuit, and a third inverter responsive to said first square wave output signal for providing a second square wave output signal having an opposite phase from said first signal, said second signal being applied to said multi-bit shift register for gating information into said multi-bit shift register, and said first signal being applied to said multi-bit shift register for gating information out of said shift register.

Claim 7

The multiphase clock signal generator recited in claim 5 wherein said multi-bit shift register comprises two bit positions, and said output logic gates comprise four logic gates for generating four multiphase clock signals.

Claim 8

The multiphase clock signal generator recited in claim 6 wherein said multi-bit shift register includes inverters for inverting the output from both bit positions of said two bit shift register, and said output logic gates comprise four NOR gates responsive to the output signals from both bit positions of said shift register and to the inverted outputs from said bit posItions, and responsive to signals fed back from the outputs of said NOR gates for generating four phase related clock signals comprising said multiphase clock signals.

Claim 9

The multiphase clock signal generator recited in claim 7 wherein two of said multiphase clock signals have a clock signal width which is twice as large as the clock signal width of the remaining two clock signals.

Claim 10

The multiphase clock signal generator recited in claim 1 wherein said RC oscillator circuit comprises first and second inverters, a resistor and a capacitor connected in series between the input and output of said second inverter, said first inverter receiving an input from a common connection between said resistor and capacitor, the output of said first inverter connected to the input to said second inverter, the output of said second inverter being connected to each bit position of said multi-bit shift register for gating information from said multi-bit shift register, and a third inverter connected to the output of said second inverter, the output of said third inverter connected to the remaining bit positions of said multi-bit shift register for gating information into said multi-bit shift register.

Claim 11

The multiphase clock signal generator recited in claim 9 wherein the outputs from each bit position of said multi-bit shift register are inverted, the outputs from each of said bit positions and the inverted outputs from said bit positions being provided as inputs to said output logic gates, said signals being generated by said RC oscillator circuit having a cycle equal to one phase of said multiphase clock signals generated by said output logic gates.

Claim 12

A multiple phase clock signal generating circuit comprising, oscillator circuit means for supplying regularly recurring signals, shift register means for receiving signals from said oscillator circuit means wherein said signals from said oscillator circuit means control the operation of said shift register means, and output means including a plurality of gate means, each of said gate means having a plurality of input terminals and an output terminal, at least one of said input terminals of each of said gate means connected to said shift register means to receive signals therefrom, the output terminals of some of said gate means connected to the other input terminals of said gate means whereby said output means produces output signals representative of the signals received from said shift register means.

Claim 13

A multiple phase clock signal generating circuit comprising, oscillator circuit means for supplying regularly recurring signals, shift register means for receiving signals from said oscillator circuit means wherein said signals from said oscillator circuit means control the operation of said shift register means, and output means including a plurality of gate means, each of said gate means having a plurality of input terminals and an output terminal, at least one of said input terminals of each of said gate means connected to said shift register means to receive signals therefrom, the output terminals of some of said gate means connected to the other input terminals of said gate means whereby said output means produces output signals representative of the signals received from said shift register means.