US3596188A
Expired / Lapsed
US
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Four-phase digital clock
Assignee: Control Data Corp
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Filing: 1969-12-03
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Granted: 1971-07-27
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Expires: 1989-12-03
Abstract
Abstract A four-phase digital clock for use in digital systems whereby an oscillator means simultaneously provides a first triangular waveshape output signal and a second substantially square waveshape output signal and a second substantially square waveshape output signal in a quadrature with respect to one another and including logic means coupled to the outputs of the oscillator means for providing the four-phase digital clock signal. The oscillator includes a Miller integrator connected in series with a high gain positive feedback amplifier the output of which is fed back to the input of the integrator. The four clock pulses are derived by sensing the positive-going high gain amplifier output, sensing the negative-going high gain amplifier output, sensing the zero crossing integrator output (positivegoing), and sensing the zero crossing integrator output (negative-going).
Inventors
- 👤 John A Hasse
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 23:03
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/15; H03K5/15013; H03K5/1506; H03K5/15073; Y; Y10; Y10S; Y10S331/00; Y10S331/03
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
89 words
A multiphase digital clock for use in digital systems, comprising: first amplifier means for providing a substantially triangular waveshape output signal; nonlinear or saturating switch means operatively associated with said first amplifier means for providing a substantially square waveshape output signal; means coupling the output of said switch means to an input of said first amplifier means for providing positive feedback to said first amplifier means; and logic means coupled to the outputs of said first amplifier means and said switch means for providing a multiphase digital clock signal.
Claim 2
Dependent Claim
89 words
A multiphase digital clock for use in digital systems, comprising: first amplifier means for providing a substantially triangular waveshape output signal; nonlinear or saturating switch means operatively associated with said first amplifier means for providing a substantially square waveshape output signal; means coupling the output of said switch means to an input of said first amplifier means for providing positive feedback to said first amplifier means; and logic means coupled to the outputs of said first amplifier means and said switch means for providing a multiphase digital clock signal.
Claim 3
Dependent Claim
28 words
A multiphase digital clock as in claim 1 wherein said triangular waveshape output signal and said square waveshape output signal are in quadrature with respect to one another.
Claim 4
Dependent Claim
93 words
A multiphase digital clock as in claim 2 wherein said logic means includes: first comparator means coupled to the output of said first amplifier means for producing a first predetermined output signal in relationship with a predetermined characteristic of said triangular waveshape output signal; second comparator means coupled to the output of said saturating switch means for producing a second predetermined output signal in relationship With a predetermined characteristic of said square waveshape output signal; and output means electrically coupled to said first and second comparator means for providing multiphase digital clock signals.
Claim 5
Dependent Claim
26 words
A digital clock as in claim 3 for providing a four-phase digital clock output wherein said saturating switch means includes a high gain positive feedback amplifier.
Claim 6
Dependent Claim
34 words
A digital clock as in claim 4 wherein said first amplifier means includes a Miller integrator having an operational amplifier and a feedback capacitor connected between the output and input of said operational amplifier.
Claim 7
Dependent Claim
86 words
A digital clock as in claim 5 wherein said output means include: gate means for gating out said clock signals; first inverter means coupled between said first capacitor means and said gate means for inverting the signal output from said first comparator means; second inverter means coupled between said second comparator means and said gate means for inverting the signal output from said second comparator means; and third inverter means respectively coupled to the outputs from said gate means for providing said four-phase digital clock output.
Claim 8
Dependent Claim
20 words
A digital clock as in claim 6 wherein said first and second comparator means each include a Schmitt trigger circuit.
Claim 9
Dependent Claim
21 words
A digital clock as in claim 7 further including: means for selectively applying a gate signal to said saturating switch means.
Claim 10
Dependent Claim
50 words
A multiphase digital clock comprising: oscillator means for simultaneously providing a first substantially triangular waveshape output signal and a second substantially square waveshape output signal in quadrature with respect to one another; and logic means coupled to the outputs of said oscillator means for providing a multiphase digital clock signal.
Claim 11
Dependent Claim
50 words
A multiphase digital clock comprising: oscillator means for simultaneously providing a first substantially triangular waveshape output signal and a second substantially square waveshape output signal in quadrature with respect to one another; and logic means coupled to the outputs of said oscillator means for providing a multiphase digital clock signal.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-07-26 | 1975-01-25 | 1975-07-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-07-26 | 1979-01-25 | 1979-07-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-07-26 | 1983-01-25 | 1983-07-27 | $7700.00 | Window Closed / Lapsed |