US3764823A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Timed true and complement generator
Assignee: International Business Machines Corp
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Filing: 1972-12-29
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Granted: 1973-10-09
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Expires: 1992-12-29
Abstract
Abstract Disclosed is a true complement generator for providing the true and complement values of an input signal as an output, in response to predetermined timing signals. A first portion of the true complement generator is a gated inverter circuit generating a complement output. A second portion of the true complement generator is a gated driver circuit generating a true output. The true and complement phases of the input signal appear at the respective output nodes during the occurrence of a first timing signal, while both output nodes are held to the same level during the occurrence of a second timing signal.
Inventors
- 👤 N Donofrio
- 👤 D Kemerer
- 👤 J Raymond
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 23:53
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/096
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
189 words
A true complement generator for providing the true and complement values of an input signal as an output, in response to predetermined timing signals, comprising: an input node; a true output node; a complement output node; first and second sources of power; first and second timing signals for providing periodic connection to said first and second sources of power; first means for generating a complement output at the complement output node, and operatively connected to said input node and responsive to input signals thereon, and also responsive to said first and second sources of power and said first and second timing signals; and second means for generating a true output at the true output node and also operatively connected to said input node and responsive to input signals thereon, and also responsive to said first and second sources of power and second timing signal, said first and second means being operatively interconnected such that during the occurrence of said first timing signal the true value of an input signal appears at the true output node and the complement value of an input signal appears on the complement output node.
Claim 2
Dependent Claim
189 words
A true complement generator for providing the true and complement values of an input signal as an output, in response to predetermined timing signals, comprising: an input node; a true output node; a complement output node; first and second sources of power; first and second timing signals for providing periodic connection to said first and second sources of power; first means for generating a complement output at the complement output node, and operatively connected to said input node and responsive to input signals thereon, and also responsive to said first and second sources of power and said first and second timing signals; and second means for generating a true output at the true output node and also operatively connected to said input node and responsive to input signals thereon, and also responsive to said first and second sources of power and second timing signal, said first and second means being operatively interconnected such that during the occurrence of said first timing signal the true value of an input signal appears at the true output node and the complement value of an input signal appears on the complement output node.
Claim 3
Dependent Claim
16 words
Apparatus as in claim 1 in which said first and second timing signals are mutually exclusive.
Claim 4
Dependent Claim
30 words
Apparatus as in claim 1 wherein said first and second means comprise: a plurality of switch means including field effect transistors each having two gaTed electrodes and a gating electrode.
Claim 5
Dependent Claim
169 words
Apparatus as in claim 3 in which said first means for generating a complement output at the complement output node is a gated inverter circuit comprising: first switch means connected between the complement output node and said second source of power and also connected to said input node; second switch means in electrical parallel with said first switch means and also connected to said second timing signal; third switch means connected in an electrical series path between said first and second sources of power, said electrical series path including the parallel connection of said first and second switch means; forming a common connection for said first, second, and third switch means; a first feedback capacitance connected between the common connection formed by said first, second and third switch means and the gating electrode of said third switch means; means for charging said capacitor during the occurrence of said second timing signal; and means for discharging said capacitor during the occurrence of said first timing signal and an input signal.
Claim 6
Dependent Claim
121 words
Apparatus as in claim 3 wherein said second means for generating a true output at the true output node is a gated driver circuit comprising: fourth switch means connected between said true output node and said second source of power and also connected to said second timing signal; fifth switch means connected in electrical parallel with said fourth switch means and also connected to said complement output node; sixth switch means including a field effect transistor having one of its gated nodes connected to the true output node and a second feedback capacitance connected between a gating electrode of said sixth switch means and said output node; and means for charging said second capacitor during the occurrence of an input signal.
Claim 7
Dependent Claim
53 words
Apparatus as in claim 3 wherein said first and second means have a common connection further comprising: a gating switch connected between said first source of power and said common connection for providing periodic connection of said common connection to said first source of power during the occurrence of said first timing signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-10-08 | 1977-04-09 | 1977-10-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-10-08 | 1981-04-09 | 1981-10-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-10-08 | 1985-04-09 | 1985-10-09 | $7700.00 | Window Closed / Lapsed |