Patent EP0426407A2 successfully refreshed from Google Patents.
US3792292A
Expired / Lapsed
US
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Three-state logic circuit
Assignee: National Semiconductor Corp
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Filing: 1972-06-16
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Granted: 1974-02-12
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Expires: 1992-06-16
Abstract
Abstract An improved three-state logic circuit for selectively providing active sourcing, active sinking or high impedance isolation of the circuit output terminal so as to develop ''''true'''' output, ''''false'''' output or third state, high impedance output signals. A first T2L data input circuit selectively drives, through a buffer stage, an active pull-up circuit and an active pull-down circuit in response to logic input signals, and a second T2L output disable circuit cooperates with the buffer stage to selectively disable the active pull-up and pull-down circuits in response to a disable signal.
Inventors
- 👤 U Priel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 15:55
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/082; H03K19/0823; H03K19/0826; H03K19/088
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
212 words
In a transistor logic circuit, first and second input signal receiving means and an output terminal, said output terminal being adapted to be connected to a driven logic circuit, first switching means connected to said first signal receiving input means and to said output terminal for selectively switching between first and second output level states on said output terminal in response to application of a signal to said first signal receiving input means, second switching means connected to said second signal receiving input means and to said first switching means to cause said first switching means to assume a condition in response to the application of a signal to said second signal receiving input means to provide a third output state on said output terminal, said third output state exhibiting a high impedance relative to the impedance of said first and second output level statEs, said first switching means including a control circuit node to which the output of said second switching means is to be applied, said second switching means being connected to said first switching means at said control circuit node, and a pair of diode junctions in said first switching means connected on opposite sides of said control circuit node and polarized for conduction toward said control circuit node.
Claim 2
Dependent Claim
212 words
In a transistor logic circuit, first and second input signal receiving means and an output terminal, said output terminal being adapted to be connected to a driven logic circuit, first switching means connected to said first signal receiving input means and to said output terminal for selectively switching between first and second output level states on said output terminal in response to application of a signal to said first signal receiving input means, second switching means connected to said second signal receiving input means and to said first switching means to cause said first switching means to assume a condition in response to the application of a signal to said second signal receiving input means to provide a third output state on said output terminal, said third output state exhibiting a high impedance relative to the impedance of said first and second output level statEs, said first switching means including a control circuit node to which the output of said second switching means is to be applied, said second switching means being connected to said first switching means at said control circuit node, and a pair of diode junctions in said first switching means connected on opposite sides of said control circuit node and polarized for conduction toward said control circuit node.
Claim 3
Dependent Claim
20 words
The apparatus of claim 1 wherein one of said diode junctions is the base to emitter junction of a transistor.
Claim 4
Dependent Claim
150 words
The apparatus of claim 1 wherein said first switching means includes, first switching transistor means for selectively connecting said output terminal to a source of current at a first potential to establish said first output level state on said output terminal, second output terminal switching transistor means for selectively connecting said output terminal to a current sink at a second potential to establish said second output level state on said output terminal, an output buffer transistor means having a first output connected to control said first output terminal switching transistor means and a second output connected to control said second output terminal switching transistor means, and said output buffer transistor means also including a control input base terminal, and means for connecting said control input base terminal of said output buffer transistor to said control node via the intermediary of an emitter to collector connection of a second buffer transistor.
Claim 5
Dependent Claim
63 words
The apparatus of claim 1 wherein said first input signal receiving means includes an input receiving transistor means having a plurality of input receiving emitter terminals, and means for connecting the output of said second switching means to one of said emitter terminals of said input receiving transistor for isolating said input receiving transistor means from its source of first input receiving signals.
Claim 6
Dependent Claim
18 words
The apparatus of claim 4 wherein said first input signal receiving transistor means includes a multiple emitter transistor.
Claim 7
Dependent Claim
292 words
In a transistor logic circuit, first and second input signal receiving means and an output terminal, said output terminal being adapted to be connected to a driven logic circuit, first switching means connected to said first signal receiving input means and to said output terminal for selectively switching between first and second output level states on said output terminal in response to application of a signal to said first signal receiving input means, second switching means connected to said second signal receiving input means and to said first switching means to cause said first switching means to assume a condition in response to the application of a signal to said second signal receiving input means to provide a third output state on said output terminal, said third output state exhibiting a high impedance relative to the impedance of said first and second output level states, said first switching means including first output switching transistor means for selectively connecting said output terminal to a source of current at a first potential to establish said first output level state on said output terminal, second output terminal switching transistor means for selectively connecting said output terminal to a current sink at a second potential to establish said second output level state on said output terminal, and output buffer transistor means having a first output connected to control said first output terminal switching transistor means and a second output connected to control said second output terminal switching transistor means, said output buffer transistor means including a control input base terminal, and means for connecting said control input base terminal of said output buffer transistor to the output of said second switching means via the intermediary of an emitter to collector connection through a second buffer transistor.
Claim 8
Dependent Claim
292 words
In a transistor logic circuit, first and second input signal receiving means and an output terminal, said output terminal being adapted to be connected to a driven logic circuit, first switching means connected to said first signal receiving input means and to said output terminal for selectively switching between first and second output level states on said output terminal in response to application of a signal to said first signal receiving input means, second switching means connected to said second signal receiving input means and to said first switching means to cause said first switching means to assume a condition in response to the application of a signal to said second signal receiving input means to provide a third output state on said output terminal, said third output state exhibiting a high impedance relative to the impedance of said first and second output level states, said first switching means including first output switching transistor means for selectively connecting said output terminal to a source of current at a first potential to establish said first output level state on said output terminal, second output terminal switching transistor means for selectively connecting said output terminal to a current sink at a second potential to establish said second output level state on said output terminal, and output buffer transistor means having a first output connected to control said first output terminal switching transistor means and a second output connected to control said second output terminal switching transistor means, said output buffer transistor means including a control input base terminal, and means for connecting said control input base terminal of said output buffer transistor to the output of said second switching means via the intermediary of an emitter to collector connection through a second buffer transistor.
Claim 9
Dependent Claim
63 words
The apparatus of claim 6 wherein said first input signal receiving means includes, an Input receiving transistor means having a plurality of input receiving emitter terminals, and means for connecting the output of said second switching means to one of said emitter terminals to said input receiving transistor for isolating said input receiving transistor means from its source of first input receiving signals.
Claim 10
Dependent Claim
18 words
The apparatus of claim 7 wherein said first input signal receiving transistor means includes a multiple emitter transistor.
Claim 11
Dependent Claim
202 words
In a transistor logic circuit, first and second input signal receiving means and an output terminal, said output terminal being adapted to be connected to a driven logic circuit, first swtiching means connected to said first signal receiving input means and to said output terminal for selectively switching between first and second output level states on said output term-inal in response to application of a signal to said first signal receiving input means, second switching means connected to said second signal receiving input means and to said first switching means to cause said first switching means to assume a condition in response to the application of a signal to said second signal receiving means to provide a third output state on said output terminal, said third output state exhibiting a high impedance relative to the impedance of said first and second output level states, said first input signal receiving means including an input receiving transistor means having a plurality of input receiving emitter terminals, and means for connecting the output of said second switching means to one of said emitter terminals of said input receiving transistor means for isolating said input receiving transistor means from its source of first input receiving signals.
Claim 12
Dependent Claim
202 words
In a transistor logic circuit, first and second input signal receiving means and an output terminal, said output terminal being adapted to be connected to a driven logic circuit, first swtiching means connected to said first signal receiving input means and to said output terminal for selectively switching between first and second output level states on said output term-inal in response to application of a signal to said first signal receiving input means, second switching means connected to said second signal receiving input means and to said first switching means to cause said first switching means to assume a condition in response to the application of a signal to said second signal receiving means to provide a third output state on said output terminal, said third output state exhibiting a high impedance relative to the impedance of said first and second output level states, said first input signal receiving means including an input receiving transistor means having a plurality of input receiving emitter terminals, and means for connecting the output of said second switching means to one of said emitter terminals of said input receiving transistor means for isolating said input receiving transistor means from its source of first input receiving signals.
Claim 13
Dependent Claim
17 words
The apparatus of claim 9 wherein said first input signal transistor means includes a multiple emitter transistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-02-11 | 1977-08-13 | 1978-02-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-02-11 | 1981-08-13 | 1982-02-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-02-11 | 1985-08-13 | 1986-02-12 | $7700.00 | Window Closed / Lapsed |