Pulse shaping circuit for use in integrated circuit networks

Claim 2

A pulse shaping circuit including in combination first circuit means having a first operating condition and a second operating condition; second circuit means having a first operating condition and a second operating condition means connecting said first circuit means to said second circuit means and operable to cause said second circuit means to operate in the second operating condition when the first circuit means is in the first operating condition and operable to cause said second circuit means to operate in the first operating condition when the first circuit means is in the second operating condition; third circuit means connected to the first and second circuit means and having a first operating condition and a second operating condition; an input terminal; first input means connected to the input terminal and to the first circuit means and operable to cause the first circuit means to operate in the first operating condition in response to the presence of a first input signal condition at the input terminal and operable to cause the first circuit means to operate in the second operating condition in response to the presence of a second input signal condition at the input terminal; second input means connected to the input terminal and to the third circuit means and operable to cause the third circuit means to operate in the first operating condition in response to the presence of the first input signal condition at the input terminal and operable to cause the third circuit means to operate in the second operating condition in response to the presence of the second input signal condition at the input terminal; an output terminal; and output circuit means connected to the second circuit means, the third circuit means, and the output terminal, and operable in a first operating condition to produce a first output condition at the output terminal when the second circuit means is in the first operating condition and the third circuit means is in the second operating condition, and operable in a second operating condition to produce a second output condition at the output terminal when the second circuit means is in the second operating condition and the third circuit means is in the first operating condition.

Claim 3

A pulse shaping circuit in accordance with claim 1 wherein said first circuit means includes a first transistor having a high conduction condition when the first circuit means is in the first operating condition and a low conduction condition when the first circuit means is in the second operating condition; said second circuit means includes a second transistor connected to the first transistor and having a high conduction condition when the second circuit means is in the first operating condition and having a low conduction condition when the second circuit means is in the second operating condition; said third circuit means includes a third transistor connected to the first and second transistors and to a first source of reference potential and having a high conduction condition when the third circuit means is in the first operating condition and having a low conduction condition when the third circuit means is in the second operating condition; and said output circuit means includes an output transistor connected to the second transistor and to the third transistor and having a high conduction condition when the output circuit means is in the first operating condition and having a low conduction condition when the output circuit means is in the second operAting condition.

Claim 4

A pulse shaping circuit in accordance with claim 2 wherein said first transistor has its base connected to the first input means, its collector connected to the base of the second transistor and coupled to a second source of reference potential, and its emitter connected to the emitter of the second transistor and to the collector of the third transistor; said second transistor has its collector coupled to the second source of reference potential, and its emitter connected to the base of the output transistor; said third transistor has its base connected to the second input means, and its emitter connected to the first source of reference potential; and said output transistor has its collector coupled to the second source of reference potential and connected to the output terminal, and its emitter connected to the first source of reference potential.

Claim 5

A pulse shaping circuit in accordance with claim 3 wherein the emitter of the first transistor, the emitter of the second transistor, and the collector of the third transistor, and the base of the output transistor are connected directly to each other; the emitter of the third transistor and the emitter of the output transistor are connected directly to the first source of reference potential; said first input means includes a first input transistor having its emitter connected to the input terminal, its base coupled through a resistance to the second source of reference potential, and its collector connected to the base of said first transistor; and said second input means includes a second input transistor having its emitter connected to the input terminal, and its base coupled through a resistance to the second source of reference potential, and a coupling transistor having its base connected to the collector of the second input transistor, its collector coupled to the second source of reference potential, and its emitter connected directly to the base of said third transistor.

Claim 6

A pulse shaping circuit including in combination a first transistor having its collector coupled to a source of reference potential; a second transistor having its collector coupled to the source of reference potential, its base connected directly to the collector of the first transistor and its emitter connected directly to the emitter of the first transistor; said second transistor being biased to a high conduction condition when the first transistor is in a low conduction condition and being biased to a low conduction condition when the first transistor is in a high conduction condition; a third transistor having its collector connected directly to the emitters of the first and second transistors and its emitter connected directly to another source of reference potential; an input terminal first input means connected to the input terminal and to the base of the first transistor and operable to bias the first transistor to the high conduction condition in response to the presence of a first input signal condition at the input terminal and operable to bias the first transistor to the low conduction condition in response to the presence of a second input signal condition at the input terminal; second input means connected to the input terminal and to the base of the third transistor and operable to bias the third transistor to a high conduction condition in response to the presence of the first input signal condition at the input terminal and operable to bias the third transistor to a low conduction condition in response to the presence of the second input signal condition a the input terminal; an output terminal; and an output transistor having its collector coupled to said first-mentioned source of reference potential and connected to the output terminal, its base connected directly to the emitters of the first and second transistors and to the collector of the third transistor, and its emitter connected directly to the other source of reference potential; said output transistor being biased to a high conduction condition to produce a first output signal level at the output terminal when the second transistor is in the high conduction condition and the third transistor is in the low conduction condition, and being biased to a low conduction condition to produce a second output signal level at the output terminal when the third transistor is in the high conduction condition.

Claim 7

A pulse shaping circuit including in combination a first transistor having its collector coupled to a source of reference potential; a second transistor having its collector coupled to the source of reference potential, its base connected directly to the collector of the first transistor and its emitter connected directly to the emitter of the first transistor; said second transistor being biased to a high conduction condition when the first transistor is in a low conduction condition and being biased to a low conduction condition when the first transistor is in a high conduction condition; a third transistor having its collector connected directly to the emitters of the first and second transistors and its emitter connected directly to another source of reference potential; an input terminal first input means connected to the input terminal and to the base of the first transistor and operable to bias the first transistor to the high conduction condition in response to the presence of a first input signal condition at the input terminal and operable to bias the first transistor to the low conduction condition in response to the presence of a second input signal condition at the input terminal; second input means connected to the input terminal and to the base of the third transistor and operable to bias the third transistor to a high conduction condition in response to the presence of the first input signal condition at the input terminal and operable to bias the third transistor to a low conduction condition in response to the presence of the second input signal condition a the input terminal; an output terminal; and an output transistor having its collector coupled to said first-mentioned source of reference potential and connected to the output terminal, its base connected directly to the emitters of the first and second transistors and to the collector of the third transistor, and its emitter connected directly to the other source of reference potential; said output transistor being biased to a high conduction condition to produce a first output signal level at the output terminal when the second transistor is in the high conduction condition and the third transistor is in the low conduction condition, and being biased to a low conduction condition to produce a second output signal level at the output terminal when the third transistor is in the high conduction condition.

Claim 8

A pulse shaping circuit in accordance with claim 5 wherein said first input means includes a first input transistor having its emitter connected to the input terminal, its base coupled through a resistance to the first-mentioned source of reference potential, and its collector connected to the base of said first transistor; said first transistor being switched from a low conduction condition to a high conduction condition when the voltage present at the input terminal increases to produce a voltage at the collector of the first input transistor which is sufficient to bias the first transistor to the high conduction condition; said first transistor being switched from the high conduction condition to the low conduction condition when the voltage present at the input terminal decreases to produce a voltage at the collector of the first input transistor which is below that sufficient to bias the first transistor to the high conduction condition; said second input means includes a second input transistor having its emitter connected to the input terminal, and its base coupled through a resistance to the first-mentioned source of reference potential, and a coupling transistor having its base connected to the collector of the second input transistor, its collector coupled to the first-mentioned source of reference potential, and its emitter connected directly to the base of said third transistor; said coupling transistor being switched from a low conduction condition to a high conduction condition causing current to flow into the base of the third transistor biasing the third transistor to the high conduction condition when the voltage present at the input terminal increases to produce a voltage at the collector of the second input transistor which is sufficient to bias the coupling transistor to the high conduction condition; and said coupling transistor being switched from the high conduction condition to the low conduction condition biasing the third transistor to the low conduction condition when the voltage present at the input terminal decreases to produce a voltage at the collector of the second input transistor which is below that sufficient to bias the coupling transistor to the high conduction condition.