US3591856A
Expired / Lapsed
US
⏱️ 0.0 years remaining
J-k master-slave flip-flop
Assignee: Texas Instruments Inc
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Filing: 1967-11-07
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Granted: 1971-07-06
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Expires: 1987-11-07
Abstract
Abstract Disclosed is a J-K master-slave flip-flop system having a simplified gating system and in which no clock pulse connections are required for the transfer transistors. Clock pulses are fed to input gates. Additional clocks may be added by tying the input gates to clock lines. The clock pulse are ANDed together at the input gate so that the J-K master-slave flip-flop system is suitable for use in large arrays.
Inventors
- 👤 Jeffrey C Kalb
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 17:17
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/286; H03K3/289; H03K3/027; H03K3/037; H03K3/0372
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
184 words
A master-slave flip-flop comprising in combination: a. first and second multiple input gate circuits, each including at least one multiple emitter transistor, said first and second gate circuits being interconnected to form a master flip-flop having two output states; b. third and fourth multiple input gate circuits, each including at least one multiple emitter transistor, said third and fourth gate circuits being interconnected to form a slave flip-flop having two output states; c. first circuit means for interconnecting said master and said slave flip-flops; and d. second and third circuit means for respectively applying plural input signals and at least one clock signal to said first and second multiple input gate circuits, said input and clock signals having at least two conditions; e. said master flip-flop includes means responsive to one condition of said input signals and one condition of said clock signal for changing the state of said master flip-flop, and said slave flip-flop includes means responsive to said master flip-flop and the other condition of said clock signal for changing the state of said slave flip-flop after said master flip-flop changes state.
Claim 2
Dependent Claim
184 words
A master-slave flip-flop comprising in combination: a. first and second multiple input gate circuits, each including at least one multiple emitter transistor, said first and second gate circuits being interconnected to form a master flip-flop having two output states; b. third and fourth multiple input gate circuits, each including at least one multiple emitter transistor, said third and fourth gate circuits being interconnected to form a slave flip-flop having two output states; c. first circuit means for interconnecting said master and said slave flip-flops; and d. second and third circuit means for respectively applying plural input signals and at least one clock signal to said first and second multiple input gate circuits, said input and clock signals having at least two conditions; e. said master flip-flop includes means responsive to one condition of said input signals and one condition of said clock signal for changing the state of said master flip-flop, and said slave flip-flop includes means responsive to said master flip-flop and the other condition of said clock signal for changing the state of said slave flip-flop after said master flip-flop changes state.
Claim 3
Dependent Claim
32 words
A master-slave flip-flop in accordance with claim 1 wherein said first circuit means includes two transistors for respectively coupling the outputs of said master flip-flop to the inputs of said slave flip-flop.
Claim 4
Dependent Claim
24 words
A master-slave flip-flop in accordance with claim 1, wherein each of said second and third circuit means includes at least one multiple emitter transistor.
Claim 5
Dependent Claim
47 words
A master-slave flip-flop in accordance with claim 1 and further including fourth circuit means for applying clear and preset signals to said master and said slave flip-flops, whereby the states of said master and slave flip-flops are selectively changed in response to said clear and present signals.
Claim 6
Dependent Claim
23 words
A master-slave flip-flop in accordance with claim 1 wherein said first, second, third and fourth multiple input gate circuits are inverting gate circuits.
Claim 7
Dependent Claim
41 words
A master-slave flip-flop in accordance with claim 5 wherein said J-K signals and clock signals are selectively coupled to said master flip-flop by fifth and sixth NAND gates, with each of said NAND gates having at least one multiple emitter transistor.
Claim 8
Dependent Claim
171 words
A master slave flip-flop comprising in combination: a. a master flip-flop comprising first and second interconnected NAND gates with each of said NAND gates having at least one multiple emitter transistor, said master flip-flop having two output states; b. a slave flip-flop comprising third and fourth interconnected NAND gates, with each of said NAND gates having at least one multiple emitter transistor, said slave flip-flop having two output states; c. circuit means for interconnecting said master and said slave flip-flops, said circuit means being responsive to J-K signals and clock signals, with each of said signals having at least a high and a low level d. the output state of said master flip-flop includes means responsive to one of said J-K signals and the high level of said clock signal for changing the state of said master flip-flop, and said slave flip-flop includes means responsive to said master flip-flop and the low level of said clock signal for changing the state of said slave flip-flop after said master flip-flop changes state.
Claim 9
Dependent Claim
171 words
A master slave flip-flop comprising in combination: a. a master flip-flop comprising first and second interconnected NAND gates with each of said NAND gates having at least one multiple emitter transistor, said master flip-flop having two output states; b. a slave flip-flop comprising third and fourth interconnected NAND gates, with each of said NAND gates having at least one multiple emitter transistor, said slave flip-flop having two output states; c. circuit means for interconnecting said master and said slave flip-flops, said circuit means being responsive to J-K signals and clock signals, with each of said signals having at least a high and a low level d. the output state of said master flip-flop includes means responsive to one of said J-K signals and the high level of said clock signal for changing the state of said master flip-flop, and said slave flip-flop includes means responsive to said master flip-flop and the low level of said clock signal for changing the state of said slave flip-flop after said master flip-flop changes state.
Claim 10
Dependent Claim
33 words
A master-slave flip-flop in accordance with claim 7 wherein said circuit means include first and second transistors for respectively coupling the outputs of said master flip-flop to the inputs of said slave flip-flop.
Claim 11
Dependent Claim
207 words
A master-slave flip-flop system comprising in combination: a. a master flip-flop circuit having cross-coupled multiple emitter transistors, said master flip-flop having two output states; b. a slave flip-flop circuit having cross-coupled multiple emitter transistors, said slave flip-flop circuit having two output states; c. first and second transfer gate circuits respectiVely coupled between the output of said master flip-flop and the input of said slave flip-flop; and d. first and second multiple input gate circuits for respectively applying plural input signals and at least one clock signal to the input of said master flip-flop, each of said input gate circuits including at least one multiple emitter transistor and said input and clock signals have at least two conditions; wherein e. said input signals are selectively applied to said first and second multiple input gate circuits and said clock signal is applied to said master flip-flop; and f. said master flip-flop includes means responsive to one condition of said input signals and one condition of said clock signal for changing the state of said master flip-flop, and said slave flip-flop includes means responsive to said master flip-flop and the other condition of said clock signal for changing the state of said slave flip-flop after said master flip-flop changes state.
Claim 12
Dependent Claim
207 words
A master-slave flip-flop system comprising in combination: a. a master flip-flop circuit having cross-coupled multiple emitter transistors, said master flip-flop having two output states; b. a slave flip-flop circuit having cross-coupled multiple emitter transistors, said slave flip-flop circuit having two output states; c. first and second transfer gate circuits respectiVely coupled between the output of said master flip-flop and the input of said slave flip-flop; and d. first and second multiple input gate circuits for respectively applying plural input signals and at least one clock signal to the input of said master flip-flop, each of said input gate circuits including at least one multiple emitter transistor and said input and clock signals have at least two conditions; wherein e. said input signals are selectively applied to said first and second multiple input gate circuits and said clock signal is applied to said master flip-flop; and f. said master flip-flop includes means responsive to one condition of said input signals and one condition of said clock signal for changing the state of said master flip-flop, and said slave flip-flop includes means responsive to said master flip-flop and the other condition of said clock signal for changing the state of said slave flip-flop after said master flip-flop changes state.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-07-05 | 1975-01-04 | 1975-07-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-07-05 | 1979-01-04 | 1979-07-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-07-05 | 1983-01-04 | 1983-07-06 | $7700.00 | Window Closed / Lapsed |