Transistor logic circuits

Claim 1

A LOGIC CIRCUIT INCLUDING IN COMBINATION AN INPUT CIRCUIT MEANS ADAPTED TO PRODUCE A SIGNAL IN RESPONSE TO A PREDETERMINED SIGNAL CONDITION AT THE INPUT THERETO, A FIRST TRANSISTOR CIRCUIT MEANS CONNECTED TO SAID INPUT CIRCUIT MEANS AND RESPONSIVE TO SAID SIGNAL TO PRODUCE SIGNALS AT FIRST AND SECOND OUTPUT CONNECTIONS, A SECOND TRANSISTOR CIRCUIT MEANS INCLUDING A SECOND TRANSISTOR CONNECTED TO THE FIRST OF SAID OUTPUT CONNECTIONS, AND OUTPUT TERMINAL, AND A SOURCE OF REFERENCE POTENTIAL, AND RESPONSIVE TO THE SIGNAL AT THE FIRST OF SAID OUTPUT CONNECTIONS TO BIAS THE SECOND TRANSISTOR TO CONDUCTION AND CHANGE THE COLTAGE LEVEL AT THE OUTPUT TERMINAL FROM A FIRST PEDETERMINED VOLTAGE LEVEL TO A SECOND PREDETERMINED VOLTAGE LEVEL, AND A THIRD TRANSISTOR CIRCUIT MEANS INCLUDING A THIRD TRANSISTOR CONNECTOR TO THE SECOND OF SAID OUTPUT CONNECTIONS AND TO SAID OUTPUT TERMINAL AND RESPONSIVE TO TERMINATION OF THE SIGNAL AT THE SECOND OF SAID OUTPUT CONNECTIONS TO BIAS THE THIRD TRANSISTOR TO CONDUCTION AND CHANGE THE VOLTAGE LEVEL AT THE OUTPUT TERMINAL FROM SAID SECOND PREDETERMINED VOLTAGE LEVEL TO SAID FIRST PREDETERMINED VOLTAGE LEVEL, AND RESPONSIVE TO RESTORATION OF SAID FIRST PREDETERMINED VOLTAGE LEVEL AT THE OUTPUT TERMINAL TO BIAS THE THIRD TRANSISTOR TO NON-CONDUCTION.