US3564281A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High speed logic circuits and method of constructing the same
Assignee: Hitachi Ltd
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Filing: 1967-12-12
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Granted: 1971-02-16
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Expires: 1987-12-12
Abstract
Abstract A logic inverter having a transistor emitter follower output circuit and an input circuit including therein a multicollector transistor or two transistors whose bases and emitters are connected in parallel with each other. In the inverter, the two collectors of the multicollector transistor or of the two transistors in the input circuit are connected to the base and the emitter, which is the output terminal, of the emitter follower transistor, respectively. A plurality of such inverters are combined in such a manner that the bases and the output terminals of the emitter follower transistors are connected in multiple to provide a logic circuit.
Inventors
- 👤 Mitio Tokunaga
- 👤 Mitsuru Kawanami
- 👤 Susumu Aikyo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 23:25
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0008; H03K19/001; H03K19/01; H03K19/013; H03K19/0136; H03K19/02; H03K19/08; H03K5/00; H03K5/01; H03K5/02
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
82 words
A high output level inverter having an output circuit of the totem pole type including a first transistor and a second transistor, said inverter comprising a series circuit of a diode and a third transistor which is connected between the base of said first transistor in said output circuit of the totem pole type and ground, the base of said third transistor being connected in parallel with the base of said second transistor in said output circuit of the totem pole type.
Claim 2
Dependent Claim
82 words
A high output level inverter having an output circuit of the totem pole type including a first transistor and a second transistor, said inverter comprising a series circuit of a diode and a third transistor which is connected between the base of said first transistor in said output circuit of the totem pole type and ground, the base of said third transistor being connected in parallel with the base of said second transistor in said output circuit of the totem pole type.
Claim 3
Dependent Claim
32 words
A high output level inverter according to claim 1, further comprising a resistor connected between a power supply and the junction point between the base of said first transistor and said diode.
Claim 4
Independent Claim
156 words
A method of constructing a high speed logic circuit comprising a plurality of inverters each having an output circuit of the totem pole type and a driving circuit therefor, each said output circuit of the totem pole type including therein a transistor which serves as an emitter follower and whose collector terminal is connected to a power supply through a resistor, characterized by constructing said driving circuit in such a manner that said driving circuit includes therein at least one transistor whose collector is operative at a level substantially same as the operating level of the emitter of said emitter follower transistor, deriving a logic terminal from said collector of said transistor included in each said driving circuit, and connecting said logic terminals in common with each other and output terminals of said output circuits in common with each other so as to afford the logic function of wired OR to said high speed logic circuit.
Claim 5
Independent Claim
156 words
A method of constructing a high speed logic circuit comprising a plurality of inverters each having an output circuit of the totem pole type and a driving circuit therefor, each said output circuit of the totem pole type including therein a transistor which serves as an emitter follower and whose collector terminal is connected to a power supply through a resistor, characterized by constructing said driving circuit in such a manner that said driving circuit includes therein at least one transistor whose collector is operative at a level substantially same as the operating level of the emitter of said emitter follower transistor, deriving a logic terminal from said collector of said transistor included in each said driving circuit, and connecting said logic terminals in common with each other and output terminals of said output circuits in common with each other so as to afford the logic function of wired OR to said high speed logic circuit.
Claim 6
Dependent Claim
102 words
A high output level inverter for use in a binary logic circuit having a power supply connected thereto, an output circuit including a first transistor and a second transistor connected in a totem pole configuration and coupled to said power supply, with the output taken from a common connection between said first and second transistors, and a driver circuit comprising a third transistor having its base and emitter connected in parallel with the base and emitter of said second transistor, whereby an auxiliary current path is provided by said drivEr circuit, so that current spikes from the power supply are substantially reduced.
Claim 7
Dependent Claim
102 words
A high output level inverter for use in a binary logic circuit having a power supply connected thereto, an output circuit including a first transistor and a second transistor connected in a totem pole configuration and coupled to said power supply, with the output taken from a common connection between said first and second transistors, and a driver circuit comprising a third transistor having its base and emitter connected in parallel with the base and emitter of said second transistor, whereby an auxiliary current path is provided by said drivEr circuit, so that current spikes from the power supply are substantially reduced.
Claim 8
Dependent Claim
35 words
A high output level inverter according to claim 4, wherein the collector of said third transistor is coupled to the base of said first transistor, said first transistor being connected in an emitter follower configuration.
Claim 9
Dependent Claim
30 words
A high output level inverter according to claim 5, wherein the collector of said third transistor is coupled to the base of said first transistor by means of a diode.
Claim 10
Dependent Claim
55 words
A high output level inverter according to claim 6, wherein said driver circuit further includes a resistor connected between the junction of said diode and the base of said first transistor and said power supply, whereby deterioration of the noise margin of said totem pole configuration of said first and second transistors is substantially reduced.
Claim 11
Dependent Claim
31 words
A high output level inverter according to claim 5, wherein the collector of said third transistor is coupled to the base of said first transistor by means of a short circuit.
Claim 12
Dependent Claim
22 words
A high output level inverter according to claim 8, wherein said second and third transistors are formed of a single multicollector transistor.
Claim 13
Dependent Claim
44 words
A binary logic circuit comprising a plurality of high output level inverters of the type recited in claim 12, having respective outputs connected in common, and further having the bases of their respective first transistors connected together, to thereby form a logical OR circuit.
Claim 14
Dependent Claim
43 words
A binary logic circuit comprising a high output level inverter of the type recited in claim 9, connected to the output of a multiemitter gate transistor which is connected in series with an emitter follower buffer circuit to thereby form a NAND circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-02-15 | 1974-08-17 | 1975-02-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-02-15 | 1978-08-17 | 1979-02-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-02-15 | 1982-08-17 | 1983-02-16 | $7700.00 | Window Closed / Lapsed |