Frequency divider

Claim 2

An integratable and programmable frequency divider comprising: a flip-flop having an input and two outputs, a fixed period generator including a multiplicity of switching stages connected between the input and the output of said fixed period generator, the input of said fixed period generator connected to the input of said flip-flop for receiving a signal, the output stage of said fixed period generator being comprised of a PNP transistor having a base, collector and emitter, said collector adaptable to be connected to a voltage power supply, said base being connected to a preceding stage in said fixed frequency generator and said emitter being connected to ground, a memory device having an input and an output, the input of said memory device being connected to the collector of said output stage transistor of said fixed period generator, the output of said memory device being connected to the input stage of said fixed period generator such that said fixed period generator is prevented from triggering when an input is applied to it before the previous fixed period is completed by said fixed period generator, and a plurality of gate circuits each having at least one input and one output, the inputs of said gate circuits being connected to the outputs of said flip-flop and said fixed period generator such that when a signal is received at the input of said flipflop and fixed period generator, an output signal is transmitted to each of the outputs of said plurality of gates, said output signal having characteristics of fixed and determinable output pulse width independent of frequency.

Claim 3

An integratable and programmable frequency divider comprising: a flip-flop having an input and two outputs, a fixed period generator including a multiplicity of switching stages connected between the input and output of said fixed period generator, the input of said fixed period generator connected to the input of said flip-flop for receiving a signal, the output stage of said fixed period generator being comprised of a PNP transistor having a base, collector and emitter, said collector adaptable to be connected to a voltage power supply, said base being connected to a preceding stage in said fixed period generator, and said emitter being connected to ground, a memory device having an input and an output, the input of said memory device being connected to the collector of said output stage transistor of said fixed period generator, the output of said memory device being connected to the input stage of said fixed period generator such that the fixed period generator is prevented from triggering when an input is applied to it before the previous fixed period is completed by said fixed period generator. a NAND circuit having two inputs and an output, and an AND circuit having two inputs and an output, the first output of said flip-flop being connected to a first input of said NAND, the second output of said flip-flop being connected to a first input of said AND, and the output of said fixed period generator being connected to the second input of said NAND and said AND, respectively, such that when a signal is received at the input of said flip-flop and fixed period generator, the frequency divider will function so as to provide a fixed and determinable output pulse width independent of frequency at each of the said respective outputs of said AND and said NAND.

Claim 4

An integratable and programmable frequency divider comprising: a flip-flop having an input and two outputs, a fixed period generator including a multiplicity of switching stages connected between the input and output of said fixed period generator, the input of said fixed period generator connected to the input of said flip-flop for receiving a signal, the output stage of said fixed period generator being comprised of a PNP transistor having a base, collector and emitter, said collector adaptable to be connected to a voltage power supply, said base being connected to a preceding stage in said fixed period generator, and said emitter being connected to ground, a memory device having an input and an output, the input of said memory device being connected to the collector of said output stage transistor of said fixed period generator, the output of said memory device being connected to the input stage of said fixed period generator such that the fixed period generator is prevented from triggering when an input is applied to it before the previous fixed period is completed by said fixed period generator. a NAND circuit having two inputs and an output, and an AND circuit having two inputs and an output, the first output of said flip-flop being connected to a first input of said NAND, the second output of said flip-flop being connected to a first input of said AND, and the output of said fixed period generator being connected to the second input of said NAND and said AND, respectively, such that when a signal is received at the input of said flip-flop and fixed period generator, the frequency divider will function so as to provide a fixed and determinable output pulse width independent of frequency at each of the said respective outputs of said AND and said NAND.

Claim 5

An integratable and programmable frequency divider according to claim 1, wherein: said memory device comprises a first, second and third PNP transistor, each having a base, collector and emitter, a first, second, third and fourth biasing resistor associated with said transistors, the emitter of said first transistor being connected to the collector of said output transistor in said fixed period generator, the base of said first transistor being connected to one end of said first resistor, the collector of said first transistor being connected to the base of said second transistor, the collector of said second transistor being connected to one end of a second resistor, the emitter of said second transistor being connected to the base of said third transistor, a third resistor connected at one of it''s ends to the collector of said third transistor, the emitter of said third transistor being connected to ground, a fourth resistor connected between the base of said third transistor and ground, the other ends of said first, second and third resistor being connected together, and the collector of said third transistor being connected to the input stage of said flip-flop.

Claim 6

A frequency divider according to claim 2, wherein, said fixed period generator is a monostable.

Claim 7

An integratable and programmable frequency divider according to claim 2, wherein: said memory device comprises a first, second and third PNP transistor, each having a base, collector and emitter, a first, second, third and fourth biasing resistor associated with said transistors, the emitter of said first transistor being connected to the collector of said output transistor in said fixed period generator, the base of said first transistor being connected to one end of said first resistor, the collector of said first transistor being connected to the base of said second transistor, the collector of said second transistor being connected to one end of a second resistor, the emitter of said second transistor being connected to the base of said third transistor, a third resistor connected at one of it''s ends to the collector of said third transistor, the emitter of said third transistor being connected to ground, a fourth resistor connected between the base of said third transistor and ground, the other ends of said first, second and third resistor being connected together, and the collector of said third transistor being connected to the input stage of said flip-flop.

Claim 8

An integratable and programmable electronic circuit comprising: a flip-flop having an input and two outputs, a fixed period generator having a multiplicity of stages including a multiple emitter input stage and an output stage, a first one of said multiple emitters being connected to the input of said flip-flop for receiving a signal, and a memory Circuit connected between the output and a second one of said multiple emitters of said fixed period generator such that the fixed period generator is prevented from triggering when an input signal is applied to it before the previous fixed period is completed by said fixed period generator.

Claim 9

An integratable and programmable electronic circuit comprising: a flip-flop having an input and two outputs, a fixed period generator having a multiplicity of stages including a multiple emitter input stage and an output stage, a first one of said multiple emitters being connected to the input of said flip-flop for receiving a signal, and a memory Circuit connected between the output and a second one of said multiple emitters of said fixed period generator such that the fixed period generator is prevented from triggering when an input signal is applied to it before the previous fixed period is completed by said fixed period generator.

Claim 10

An integratable and programmable electronic circuit according to claim 6, further including: a NAND circuit having two inputs and an output, and an AND circuit having two inputs and an output, the first output of said flip-flop being connected to a first input of said NAND, the second output of said flip-flop being connected to the first input of said AND, and the output of said fixed period generator being connected to the second input of said NAND and said AND, respectively, such that when a signal is applied to the input of said flip-flop and said fixed period generator an output signal will be transmitted to each of the outputs of said AND and NAND, said output signals having characteristics of a fixed and determinable output pulse width independent of frequency.