DRAM with reduced-test-time-mode

Claim 2

A semiconductor memory device, comprising: a plurality of address lines, a plurality of memory cells coupled with said address lines, a test request detection circuit means to produce a test signal if a voltage has been applied on a most significant one of said address lines which is higher than a range of voltages supplied under ordinary operation conditions, means responsive to the test signal for causing writing of data, which has been supplied to the semiconductor memory device, into a plurality of memory cells simultaneously, and thereafter, simultaneously reading data from said plurality of memory cells, and means for judging whether or not the data read from said plurality of memory cells coincides with the data originally supplied to the semiconductor memory device.

Claim 3

A device according to claim 1, wherein said judging means comprises a plurality of judging circuits receiving the data having been supplied to the semiconductor memory device and the data read out of the respective memory cells.

Claim 4

A device according to claim 2, wherein each of the judging circuits comprises an Exclusive-OR circuit whose output is at "1" if the data read out of the corresponding memory cell does not coincide with the data having been supplied to the semiconductor memory device.

Claim 5

A device according to claim 3, wherein said judging means further comprises an OR circuit receiving the output of the Exclusive-OR circuit to produce an error detection signal if any of the Exclusive-OR circuit produces an output of "1".

Claim 6

A device according to claim 2, wherein said judging means outputs results indicating whether data read out from ones of the memory cells coincides with data originally supplied to the semiconductor memory device onto an external terminal.

Claim 7

A device according to claim 1, wherein each of the memory cells comprises a field effect transistor.

Claim 8

The memory of claim 1, wherein said memory is a dynamic random access memory (DRAM).

Claim 9

The memory of claim 1, wherein said test request detection circuit contains plural FETs connected together to provide an effective threshold voltage which is outside of the range of voltages supplied under ordinary operation conditions.

Claim 10

A semiconductor memory device, comprising: at least one array of memory cells coupled with said address lines; peripheral logic connected to select ones of said memory cells for reading or writing in accordance with externally received cell address signals, wherein ones of said cell address signals are sequentially multiplexed onto a set of address lines which are less than the number needed to uniquely identify one of said cells; a test request detection circuit means to produce a test signal if a voltage has been applied on a most significant one of said address lines which is higher than a range of voltages supplied under ordinary operation conditions; a parallel addressing circuit, which causes said peripheral logic to write externally supplied data into a plurality of said memory cells simultaneously, when said test detection circuit indicates that a high voltage has been received; and at least one judging circuit, which ascertains whether a memory cell has correctly repeated the data value which was stored in it.

Claim 11

A semiconductor memory device, comprising: at least one array of memory cells coupled with said address lines; peripheral logic connected to select ones of said memory cells for reading or writing in accordance with externally received cell address signals, wherein ones of said cell address signals are sequentially multiplexed onto a set of address lines which are less than the number needed to uniquely identify one of said cells; a test request detection circuit means to produce a test signal if a voltage has been applied on a most significant one of said address lines which is higher than a range of voltages supplied under ordinary operation conditions; a parallel addressing circuit, which causes said peripheral logic to write externally supplied data into a plurality of said memory cells simultaneously, when said test detection circuit indicates that a high voltage has been received; and at least one judging circuit, which ascertains whether a memory cell has correctly repeated the data value which was stored in it.

Claim 12

A semiconductor memory device, comprising: a plurality of subarrays of memory cells; peripheral logic connected to select ones of said memory cells for reading or writing in accordance with externally received cell address signals, wherein ones of said cell address signals are sequentially multiplexed onto a set of address lines which are less than the number needed to uniquely identify one of said cells; a test request detection circuit means to produce a test signal if a voltage has been applied on a most significant one of said address lines which is higher than a range of voltages supplied under ordinary operation conditions; a parallel addressing circuit, which causes said peripheral logic to write externally supplied data into a plurality of said memory cells, in plural respective ones of said subarrays, simultaneously, at locations determined by data on the ones of said address lines on which said voltage was not applied, when said test detection circuit indicates that a high voltage has been received; and at least one judging circuit, which ascertains whether a memory cell has correctly repeated the data value which was stored in it.

Claim 13

A semiconductor memory device, comprising: a plurality of subarrays of memory cells; peripheral logic connected to select ones of said memory cells for reading or writing in accordance with externally received cell address signals, wherein ones of said cell address signals are sequentially multiplexed onto a set of address lines which are less than the number needed to uniquely identify one of said cells; a test request detection circuit means to produce a test signal if a voltage has been applied on a most significant one of said address lines which is higher than a range of voltages supplied under ordinary operation conditions; a parallel addressing circuit, which causes said peripheral logic to write externally supplied data into a plurality of said memory cells, in plural respective ones of said subarrays, simultaneously, at locations determined by data on the ones of said address lines on which said voltage was not applied, when said test detection circuit indicates that a high voltage has been received; and at least one judging circuit, which ascertains whether a memory cell has correctly repeated the data value which was stored in it.

Claim 14

The memory of claim 9, wherein said test request detection circuit contains plural FETs connected together to provide an effective threshold voltage which is outside of the range of voltages supplied under ordinary operation conditions.

Claim 15

The memory of claim 10, wherein said test request detection circuit contains plural FETs connected together to provide an effective threshold voltage which is outside of the range of voltages supplied under ordinary operation conditions.

Claim 16

The memory of claim 9, wherein said parallel addressing circuit causes said peripheral logic to write externally supplied data into a plurality of said memory cells at locations determined by data on ones of said address lines on which said voltage was not applied. .Iadd.

Claim 17

A semiconductor memory device, comprising: (a) a plurality of address lines; (b) a plurality of memory cells coupled with said address lines; (c) a test request detection circuit means to produce a test signal upon receipt of a higher voltage which is higher than a range of voltages applied under ordinary operation conditions, said test request detection circuit means comprising (i) an input terminal for receiving said higher voltage, (ii) a series connection of a plurality of MOSTs, each having a gate and a drain, wherein said series connection of MOSTs is connected at a first end to said input terminal, and wherein each of said MOSTs has its gate and drain coupled together, (iii) a latch circuit, coupled to a second end of second series connection of MOSTs at a first end of said latch circuit, (iv) an inverted test signal generating circuit responsive to an output end of said latch circuit, wherein said test signal generating circuit produces an inverted test signal, and (v) a reset circuit for resetting said latch circuit; (d) means responsive to the test signal for causing writing of data, which has been supplied to the semiconductor memory device, into a plurality of memory cells simultaneously, and thereafter, simultaneously reading data from said plurality of memory cells; and (e) means for judging whether or not the data read from each of said plurality of memory cells coincides with one another. .Iaddend. .Iadd.

Claim 18

A semiconductor memory device, comprising: (a) a plurality of address lines; (b) a plurality of memory cells coupled with said address lines; (c) a test request detection circuit means to produce a test signal upon receipt of a higher voltage which is higher than a range of voltages applied under ordinary operation conditions, said test request detection circuit means comprising (i) an input terminal for receiving said higher voltage, (ii) a series connection of a plurality of MOSTs, each having a gate and a drain, wherein said series connection of MOSTs is connected at a first end to said input terminal, and wherein each of said MOSTs has its gate and drain coupled together, (iii) a latch circuit, coupled to a second end of second series connection of MOSTs at a first end of said latch circuit, (iv) an inverted test signal generating circuit responsive to an output end of said latch circuit, wherein said test signal generating circuit produces an inverted test signal, and (v) a reset circuit for resetting said latch circuit; (d) means responsive to the test signal for causing writing of data, which has been supplied to the semiconductor memory device, into a plurality of memory cells simultaneously, and thereafter, simultaneously reading data from said plurality of memory cells; and (e) means for judging whether or not the data read from each of said plurality of memory cells coincides with one another. .Iaddend. .Iadd.

Claim 19

The semiconductor memory device of claim 14, wherein said latch circuit comprises two MOSTs cross-coupled with each other, wherein each of said MOSTs contain a gate, and wherein the gate of one of said MOSTs is coupled to said second end of said series connection of MOSTs. .Iaddend. .Iadd.16. The semiconductor memory device of claim 15, wherein said reset circuit comprises at least one MOST which couples the gate of at least one of said two MOSTs to a power supply node. .Iaddend. .Iadd.17. A semiconductor memory device, comprising: at least one array of memory cells coupled with said address lines; peripheral logic connected to select ones of said memory cells for reading or writing in accordance with externally received cell address signals, wherein ones of said cell address signals are sequentially multiplexed onto a set of address lines which are less than the number need to uniquely identify one of said cells; a test request detection circuit means to produce a test signal if a voltage has been applied on a most significant one of said address lines which is higher than a range of voltages supplied under ordinary operation conditions; a parallel addressing circuit responsive to the test signal for causing said peripheral logic to write externally supplied data into a plurality of said memory cells simultaneously; and at least one judging circuit, which ascertains whether said plurality of memory cells have correctly repeated the data value which was stored in them.