Electrically programmable non-volatile semiconductor memory device

Claim 2

An electrically programmable non-volatile semiconductor memory device which comprises a plurality of word lines (WL), a plurality of bit lines (BL) and cell transistors each having a-control gate (CG) connected to one of the word lines, a drain (D) connected to one of the bit lines and a floating gate (FG) for storing an electric charge therein, the electrically programmable non-volatile semiconductor device being characterized by at least one additional circuit (Z 1 , Z 2 , Z 3 ) for placing, at the time of testing the device, all the said word lines and/or all the said bit lines in a selected state at the same time.

Claim 3

An electrically programmable non-volatile semiconductor memory device comprising: a first group of addressbuffers(AB5-AB12); a row decoder (RD) which is connected to the first group of address buffers and which has its output connected to a plurality of word lines (WL); a second group of address buffers (AB o -AB 4 ); a column decoder (CD) which is connected to the second group of address buffers and which has its output connected to a plurality of column output lines (C o -C 31 ); a power down means for placing the first and second group of address buffers in the power down mode by applying a power down mode signal (PD); a plurality of bit lines (BL) which are selected by the output of the column decoder output lines; a memory array (MCA) of cell transistors which are arranged at the cross-points of the word lines and the bit lines, each memory array having a control gate (CG) connected to the word line, a drain (D) connected to the bit line and a floating region (FG) for storing electric charges, the information "0" being written in the cell transistor by placing the selected word line and the selected bit line at a high potential at the same time, and the information "1" being written in the cell transistor by placing the selected word line at a high potential and the selected bit line at a low potential; and characterized in that the electrically programmable non-volatile semiconductor memory device further comprises at least one additional circuit (z 1 ,z 2 z 3 ) for placing, at the test time, all the said word lines and/or all the said bit lines in a selected state or a non-selected state at the same time.

Claim 4

An electrically programmable non-volatile semiconductor memory device comprising: a first group of addressbuffers(AB5-AB12); a row decoder (RD) which is connected to the first group of address buffers and which has its output connected to a plurality of word lines (WL); a second group of address buffers (AB o -AB 4 ); a column decoder (CD) which is connected to the second group of address buffers and which has its output connected to a plurality of column output lines (C o -C 31 ); a power down means for placing the first and second group of address buffers in the power down mode by applying a power down mode signal (PD); a plurality of bit lines (BL) which are selected by the output of the column decoder output lines; a memory array (MCA) of cell transistors which are arranged at the cross-points of the word lines and the bit lines, each memory array having a control gate (CG) connected to the word line, a drain (D) connected to the bit line and a floating region (FG) for storing electric charges, the information "0" being written in the cell transistor by placing the selected word line and the selected bit line at a high potential at the same time, and the information "1" being written in the cell transistor by placing the selected word line at a high potential and the selected bit line at a low potential; and characterized in that the electrically programmable non-volatile semiconductor memory device further comprises at least one additional circuit (z 1 ,z 2 z 3 ) for placing, at the test time, all the said word lines and/or all the said bit lines in a selected state or a non-selected state at the same time.

Claim 5

An electrically programmable non-volatile semiconductor memory device according to claim 2, wherein a first additional circuit.(Z 1 ), which, in the test time, place all the said word lines at the selected state at the same time, is connected to a first address buffer (AB 5 ) included in the first group of address buffers; a second additional circuit (Z 2 ), which, in the test time, places all of said bit lines at the selected state at the same time, is connected to a second address buffer (AB ) included in the second group of address buffers; and a third additional circuit (Z 3 ) which, in the test time, places all the said word lines at the non-selected state at the same time, is connected to a third address buffer (A 12 ) included in the first group of address buffers.

Claim 6

An electrically programmable non-volatile semiconductor memory device according to claim 3, wherein the first additional circuit (Z 1 , figure 6) comprises a first inverter (Q 10 , Q 11 ) which is controlled by the input in the same way as the input of the first address buffer (A 5 ); a second inverter (C 12 -Q 14 ) which is connected to the output of said first inverter and which is controlled by either the output of said first inverter or said power down mode signal ( PD ); and a third inverter (Q 15' Q 16 ) which controls the first address buffer (Fig. 4) by the output of the second inverter, so that the first address buffer places all the said word lines of the row decoder in the selected state by the output of said third inverter; the second additional circuit (Z 2 ) comprises a fourth inverter which is controlled by the input in the same way as the input of the second address buffer; a fifth inverter which is connected to the output of the fourth inverter and which is controlled by either the output of the fourth inverter or the power down mode signal; and a sixth inverter which controls the second address buffer by the output of the fifth inverter, so that the second address buffer places all the said bit lines of the column decoder in the selected state by the output of the sixth inverter; and the third additional circuit (Z 3 ) comprises a seventh inverter which is controlled by the input in the same way as the input of the third address buffer; an eighth inverter which is connected to the output of the seventh inverter and which is controlled by either the output of the seventh inverter or the power down mode signal; and a-ninth inverter which controls the third address buffer by the output of the eighth inverter, so that the third address buffer places all the said word lines of the row decoder in the non-selected state by the output of the ninth inverter.

Claim 7

An electrically programmable non-volatile semiconductor memory device according to claim 1, wherein (Figures 8, 9) all the bit lines are divided into N bit line groups (BLG 0 -BLG 3 ), each group containing M bit lines (BL o -BL 8 ), N first column selecting gates (G 4O -G 43 ) are disposed to correspond to the respective bit line groups, M second column selecting gates (G o -G 7 ) are disposed in each bit line group to correspond to the respective bit lines, the column decoder is divided into a first column decoder (CD l ) and a second column decoder (CD 2 ), the first column decoder is arranged so that the first column selecting gates can be selected individually or simultaneously by the output of the first column decoder, the second column decoder is arranged so that one second column selecting gate in each bit line group and N second column gates as a whole can be selected simultaneously, and so that the additional circuit is connected to one of address buffers connected to the input of the first column decoder so that the additional circuit is disposed to simultaneously select N of the first column selecting gates by the first column decoder at the test time when the information "0" is written in all the cells.

Claim 8

An electrically programmable non-volatile semiconductor memory device according to claim 5, wherein the additional circuit comprises a first inverter (Q 30' Q 31' Fig. 12), which is controlled by the input in the same way as the input of the address buffer; a second inverter (Q32-034), which is connected to the output of the first inverter and which is controlled by either the output of the first inverter or the power down mode signal; and a third inverter (Q 35 -Q 36 ) which selects the first column selection gates at the same time by the output of the second inverter.