Two square memory cells

Claim 2

A memory comprising a semiconductor substrate having a major surface and a trench disposed therein having a longitudinal axis, storage means disposed .Iadd.solely .Iaddend.on a given sidewall of said trench, switching means having a control element .Iadd.disposed solely on said given sidewall of said trench .Iaddend.and a current carrying element disposed on said given sidewall of said trench between said storage means and said major surface of said substrate and coupled to said storage means, said storage means and said switching means being completely formed within a surface area no greater than approximately two lithographic squares, a first electrically conductive line disposed .Iadd.solely .Iaddend.on said given sidewall in contact with said control element of said switching means and having a longitudinal axis arranged parallel to the longitudinal axis of said trench, and a second electrically conductive line disposed on said major surface of said semiconductor substrate in contact with said current carrying .[.electrode.]. .Iadd.element .Iaddend.of said switching means and having a longitudinal axis arranged orthogonal to the longitudinal axis of said trench.

Claim 3

A memory as set forth in claim 1 wherein said storage means is a capacitor and said switching means is a field effect transistor.

Claim 4

A memory array comprising a semiconductor substrate having a major surface and a trench formed therein, first and second spaced apart storage means disposed on a first sidewall of said trench, third and fourth spaced apart storage means disposed on a second sidewall of said trench, first and second .Iadd.spaced apart .Iaddend.switching means disposed .Iadd.solely .Iaddend.on said first sidewall .Iadd.of said trench and separated by a portion of said first sidewall of said trench which provides neither a storage nor a switching function, said first and second switching means being arranged .Iaddend.between said first and second storage means, respectively, and major surface of said substrate, third and fourth .Iadd.spaced apart .Iaddend.switching means disposed .Iadd.solely .Iaddend.on said second sidewall .Iadd.of said trench and separated by a discrete portion of said second sidewall of said trench, said third and fourth switching means being arranged .Iaddend.between said third and fourth storage means, respectively, and said major surface of said substrate, each of said first, second, third, and fourth switching means being completely formed within a surface area no greater than approximately two lithographic squares, first means disposed .[.within.]. .Iadd.on said discrete portion of said first sidewall of .Iaddend.said trench .Iadd.between said first and second switching means .Iaddend.for interconnecting control elements of said first and second switching means, second means disposed .[.within.]. .Iadd.on said discrete portion of said second sidewall of .Iaddend.said trench .Iadd.between said third and fourth switching means .Iaddend.for interconnecting control elements of said third and fourth switching means, and first and second electrically conductive lines disposed on the major surface of said substrate, said first conductive line being connected to said first and third switching means and said second conductive line being connected to said second and fourth switching means.

Claim 5

A memory array comprising a semiconductor substrate having a major surface and a trench formed therein, first and second spaced apart storage means disposed on a first sidewall of said trench, third and fourth spaced apart storage means disposed on a second sidewall of said trench, first and second .Iadd.spaced apart .Iaddend.switching means disposed .Iadd.solely .Iaddend.on said first sidewall .Iadd.of said trench and separated by a portion of said first sidewall of said trench which provides neither a storage nor a switching function, said first and second switching means being arranged .Iaddend.between said first and second storage means, respectively, and major surface of said substrate, third and fourth .Iadd.spaced apart .Iaddend.switching means disposed .Iadd.solely .Iaddend.on said second sidewall .Iadd.of said trench and separated by a discrete portion of said second sidewall of said trench, said third and fourth switching means being arranged .Iaddend.between said third and fourth storage means, respectively, and said major surface of said substrate, each of said first, second, third, and fourth switching means being completely formed within a surface area no greater than approximately two lithographic squares, first means disposed .[.within.]. .Iadd.on said discrete portion of said first sidewall of .Iaddend.said trench .Iadd.between said first and second switching means .Iaddend.for interconnecting control elements of said first and second switching means, second means disposed .[.within.]. .Iadd.on said discrete portion of said second sidewall of .Iaddend.said trench .Iadd.between said third and fourth switching means .Iaddend.for interconnecting control elements of said third and fourth switching means, and first and second electrically conductive lines disposed on the major surface of said substrate, said first conductive line being connected to said first and third switching means and said second conductive line being connected to said second and fourth switching means.

Claim 6

A memory array as set forth in claim 3 wherein said storage means are capacitors and said switching means are field effect transistors.

Claim 7

A memory comprising a semiconductor substrate having a major surface and a trench disposed therein, a first storage capacitor disposed .Iadd.solely .Iaddend.on a first sidewall of said trench, said capacitor including a storage node disposed within said semiconductor substrate, a plate disposed within said trench and a dielectric layer interposed between said storage node and said plate, first field effect transistor having a control element disposed .Iadd.solely .Iaddend.on said first sidewall of said trench between said storage capacitor and said major surface of said substrate, .Iadd.said first storage capacitor and said first field effect transistor being completely formed within a surface area no greater than approximately two lithographic squares, .Iaddend. a first electrically conductive line disposed within said trench .Iadd.solely .Iaddend.along .[.a.]. .Iadd.said first .Iaddend.sidewall thereof connected to said control element, and a second electrically conductive line disposed on said major surface of said substrate orthogonal to said first .Iadd.electrically conductive .Iaddend.line in contact with a current carrying electrode of said transistor.

Claim 8

A memory comprising a semiconductor substrate having a major surface and a trench disposed therein, a first storage capacitor disposed .Iadd.solely .Iaddend.on a first sidewall of said trench, said capacitor including a storage node disposed within said semiconductor substrate, a plate disposed within said trench and a dielectric layer interposed between said storage node and said plate, first field effect transistor having a control element disposed .Iadd.solely .Iaddend.on said first sidewall of said trench between said storage capacitor and said major surface of said substrate, .Iadd.said first storage capacitor and said first field effect transistor being completely formed within a surface area no greater than approximately two lithographic squares, .Iaddend. a first electrically conductive line disposed within said trench .Iadd.solely .Iaddend.along .[.a.]. .Iadd.said first .Iaddend.sidewall thereof connected to said control element, and a second electrically conductive line disposed on said major surface of said substrate orthogonal to said first .Iadd.electrically conductive .Iaddend.line in contact with a current carrying electrode of said transistor.

Claim 9

A memory as set forth in claim 5 further including a second storage capacitor disposed .Iadd.solely .Iaddend.on a second sidewall of said trench, and a second field effect transistor disposed .Iadd.solely .Iaddend.on said second sidewall of said trench between said second storage capacitor and said major surface of said substrate, .Iadd.said second storage capacitor and said second field effect transistor being completely formed within a surface area no greater than approximately two lithographic squares, .Iaddend. said .Iadd.second .Iaddend.electrically conductive line being in contact with a current carrying electrode of said second transistor.

Claim 10

A memory array comprising a semiconductor substrate having a major surface and a trench formed therein, first and second spaced apart storage capacitors disposed .Iadd.solely .Iaddend.on a first sidewall of said trench, third and fourth spaced apart storage capacitors disposed .Iadd.solely .Iaddend.on a second sidewall of said trench, first and second .Iadd.spaced apart .Iaddend.field effect transistors disposed .Iadd.solely .Iaddend.on said first sidewall .Iadd.of said trench and separated by a discrete portion of said first sidewall of said trench, said first and second switching means being arranged .Iaddend.between said first and second storage capacitors, respectively, and said major surface of said substrate, third and fourth .Iadd.spaced apart .Iaddend.field effect transistors disposed .Iadd.solely .Iaddend.on said second sidewall .Iadd.of said trench and separated by a discrete portion of said second sidewall of said trench, said third and fourth switching means being arranged .Iaddend.between said third and fourth storage capacitors, respectively, and said major surface of said substrate, .Iadd.each of said first, second, third, and fourth switching means being completely formed within a surface area no greater than approximately two lithographic squares, .Iaddend. a first word line disposed .[.within.]. .Iadd.on said discrete portion of said first sidewall of .Iaddend.said trench .Iadd.between said first and second switching means for .Iaddend.interconnecting gate electrodes of said first and second field effect transistors, a second word line disposed .[.within.]. .Iadd.on said discrete portion of said second sidewall of .Iaddend.said trench .Iadd.between said third and fourth switching means for .Iaddend.interconnecting gate electrodes of said third and fourth field effect transistors, and first and second bit/sense lines disposed on the major surface of said substrate, said first bit/sense line being connected to current carrying electrodes of said first and third field effect transistors and said second bit/sense line being connected to current carrying electrodes of said second and fourth field effect transistors.

Claim 11

A memory array comprising a semiconductor substrate having a major surface and a trench formed therein, first and second spaced apart storage capacitors disposed .Iadd.solely .Iaddend.on a first sidewall of said trench, third and fourth spaced apart storage capacitors disposed .Iadd.solely .Iaddend.on a second sidewall of said trench, first and second .Iadd.spaced apart .Iaddend.field effect transistors disposed .Iadd.solely .Iaddend.on said first sidewall .Iadd.of said trench and separated by a discrete portion of said first sidewall of said trench, said first and second switching means being arranged .Iaddend.between said first and second storage capacitors, respectively, and said major surface of said substrate, third and fourth .Iadd.spaced apart .Iaddend.field effect transistors disposed .Iadd.solely .Iaddend.on said second sidewall .Iadd.of said trench and separated by a discrete portion of said second sidewall of said trench, said third and fourth switching means being arranged .Iaddend.between said third and fourth storage capacitors, respectively, and said major surface of said substrate, .Iadd.each of said first, second, third, and fourth switching means being completely formed within a surface area no greater than approximately two lithographic squares, .Iaddend. a first word line disposed .[.within.]. .Iadd.on said discrete portion of said first sidewall of .Iaddend.said trench .Iadd.between said first and second switching means for .Iaddend.interconnecting gate electrodes of said first and second field effect transistors, a second word line disposed .[.within.]. .Iadd.on said discrete portion of said second sidewall of .Iaddend.said trench .Iadd.between said third and fourth switching means for .Iaddend.interconnecting gate electrodes of said third and fourth field effect transistors, and first and second bit/sense lines disposed on the major surface of said substrate, said first bit/sense line being connected to current carrying electrodes of said first and third field effect transistors and said second bit/sense line being connected to current carrying electrodes of said second and fourth field effect transistors.

Claim 12

A dynamic random access memory comprising: a semiconductor substrate having a major surface and a trench having a longitudinal axis formed therein, first and second spaced apart storage capacitors disposed .Iadd.solely .Iaddend.along a first sidewall of said trench, first and second spaced apart bit/sense diffusion regions disposed at the surface of said substrate, and a word line disposed .[.within.]. .Iadd.solely along said first sidewall of .Iaddend.said trench along the longitudinal axis thereof and insulated from said first sidewall of said trench between said first and second .Iadd.spaced apart storage .Iaddend.capacitors and said first and second .Iadd.spaced apart .Iaddend.bit/sense diffusion regions, respectively.Iadd., so as to define first and second memory cells, each comprising a storage capacitor and a field effect transistor, and each being completely formed within a surface area no greater than approximately two lithographic squares.Iaddend..

Claim 13

A dynamic random access memory comprising: a semiconductor substrate having a major surface and a trench having a longitudinal axis formed therein, first and second spaced apart storage capacitors disposed .Iadd.solely .Iaddend.along a first sidewall of said trench, first and second spaced apart bit/sense diffusion regions disposed at the surface of said substrate, and a word line disposed .[.within.]. .Iadd.solely along said first sidewall of .Iaddend.said trench along the longitudinal axis thereof and insulated from said first sidewall of said trench between said first and second .Iadd.spaced apart storage .Iaddend.capacitors and said first and second .Iadd.spaced apart .Iaddend.bit/sense diffusion regions, respectively.Iadd., so as to define first and second memory cells, each comprising a storage capacitor and a field effect transistor, and each being completely formed within a surface area no greater than approximately two lithographic squares.Iaddend..

Claim 14

A dynamic random access memory as set forth in claim 8 further including first and second bit/sense lines connected to said first and second bit/sense diffusion regions, respectively, and arranged orthogonal to the direction of said trench.

Claim 15

A dynamic random access memory as set forth in claim 9 wherein said trench has a second sidewall opposing said first sidewall and further including: third and fourth spaced apart storage capacitors disposed .Iadd.solely .Iaddend.along said second sidewall, third and fourth spaced apart bit/sense diffusion regions disposed at the surface of said substrate, and a second word line disposed .Iadd.solely .Iaddend.along said second sidewall between said third and fourth .Iadd.spaced apart storage .Iaddend.capacitors and said third and fourth .Iadd.spaced apart .Iaddend.bit/sense diffusion regions, respectively, .Iadd.so as to define third and fourth memory cells, each comprising a storage capacitor and a field effect transistor, and each being completely formed within a surface area no greater than approximately two lithographic squares, .Iaddend. said first and second bit/sense lines being connected to said third and fourth bit/sense diffusion regions, respectively.

Claim 16

A dynamic random access memory as set forth in claim 8 wherein each of said storage capacitors includes a diffusion region disposed in said first sidewall and a conductive plate disposed within said trench insulated from said diffusion regions.

Claim 17

A dynamic random access memory as set forth in claim 11 further including an insulation layer disposed on said conductive plate between said word line and said conductive plate.

Claim 18

A dynamic random access memory as set forth in claim 11 wherein said conductive plate is made of doped polysilicon and said word line is made of a silicide.

Claim 19

A dynamic random access memory as set forth in claim 10 wherein each of said storage capacitors includes a diffusion region disposed in one of said first and second sidewalls and a conductive plate disposed within said trench insulated from said diffusion regions.

Claim 20

A dynamic random access memory as set forth in claim 14 further including an insulation layer disposed on said conductive plate between said word lines and said conductive plate.

Claim 21

A dynamic random access memory as set forth in claim 14 wherein said conductive plate is made of doped polysilicon, said word lines are made of doped polysilicon and said bit/sense lines are made of copper-doped aluminum, and further including an insulating medium disposed between said first and second word lines.

Claim 22

A dynamic random access memory as set forth in claim 16 wherein said insulating medium is polyimide.

Claim 23

A dynamic random access memory .[.as set forth in claim 8 further including.]. .Iadd.comprising: a semiconductor substrate having a major surface and a trench having a longitudinal axis formed therein, first and second spaced apart storage capacitors disposed solely along a first sidewall of said trench, first and second spaced apart bit/sense diffusion regions disposed at the surface of said substrate, and a word line disposed solely along said first sidewall of said trench along the longitudinal axis thereof and insulated from said first sidewall of said trench between said first and second spaced apart storage capacitors and said first and second spaced apart bit/sense diffusion regions, respectively, so as to define first and second memory cells, each comprising a storage capacitor and a field effect transistor, and each being completely formed within a surface area no greater than approximately two lithographic squares, and .Iaddend. a thick layer of insulation disposed on said first sidewall between said first and second storage capacitors and between said first and second bit/sense diffusion regions.

Claim 24

A memory comprising a semiconductor substrate having a major surface and a trench disposed therein having a longitudinal axis, first and second .Iadd.spaced apart .Iaddend.storage means disposed .Iadd.solely .Iaddend.on a first sidewall of said trench, first and second .Iadd.spaced apart .Iaddend.switching means each having a control element .Iadd.disposed solely on said first sidewall of said trench, .Iaddend.and a current carrying element.[.,.]. disposed on said first sidewall of said trench.Iadd., .Iaddend.between said first and second .Iadd.spaced apart .Iaddend.storage means, respectively, and said major surface of said substrate and coupled to said respective .Iadd.spaced apart .Iaddend.storage means, .Iadd.said first and second spaced apart switching means being completely formed within a combined surface area no greater than approximately two lithographic squares, .Iaddend. a first electrically conductive line disposed .[.on.]. .Iadd.solely along .Iaddend.said first sidewall in contact with the control elements of said first and second switching means and having a longitudinal axis arranged parallel to the longitudinal axis of said trench, and second and third electrically conductive lines disposed on said major surface of said semiconductor substrate in contact with said current carrying electrode of said first and second switching means, respectively, and each having a longitudinal axis arranged orthogonal to the longitudinal axis of said trench.

Claim 25

A memory comprising a semiconductor substrate having a major surface and a trench disposed therein having a longitudinal axis, first and second .Iadd.spaced apart .Iaddend.storage means disposed .Iadd.solely .Iaddend.on a first sidewall of said trench, first and second .Iadd.spaced apart .Iaddend.switching means each having a control element .Iadd.disposed solely on said first sidewall of said trench, .Iaddend.and a current carrying element.[.,.]. disposed on said first sidewall of said trench.Iadd., .Iaddend.between said first and second .Iadd.spaced apart .Iaddend.storage means, respectively, and said major surface of said substrate and coupled to said respective .Iadd.spaced apart .Iaddend.storage means, .Iadd.said first and second spaced apart switching means being completely formed within a combined surface area no greater than approximately two lithographic squares, .Iaddend. a first electrically conductive line disposed .[.on.]. .Iadd.solely along .Iaddend.said first sidewall in contact with the control elements of said first and second switching means and having a longitudinal axis arranged parallel to the longitudinal axis of said trench, and second and third electrically conductive lines disposed on said major surface of said semiconductor substrate in contact with said current carrying electrode of said first and second switching means, respectively, and each having a longitudinal axis arranged orthogonal to the longitudinal axis of said trench.

Claim 26

A memory comprising a semiconductor substrate having a major surface and a trench disposed therein having first and second opposing sidewalls and a longitudinal axis, first and second .Iadd.spaced apart .Iaddend.storage means disposed .Iadd.solely .Iaddend.on a first sidewall of said trench, first and second .Iadd.spaced apart .Iaddend.switching means each having a control element .Iadd.disposed solely on said first sidewall of said trench .Iaddend.and a current carrying element, .[.disposed on said first sidewall of said trench.]. .Iadd.said first and second switching means being separated by a portion of said first sidewall of said trench which provides an isolation function, said first and second switching means being arranged .Iaddend.between said first and second storage means, respectively, and said major surface of said substrate and coupled to said respective storage means, .Iadd.each of said first and second spaced apart switching means being completely formed within a surface area no greater than approximately two lithographic squares, .Iaddend. a first electrically conductive line disposed .[.on.]. .Iadd.solely along .Iaddend.said first sidewall .Iadd.of said trench between said first and second switching means .Iaddend.in contact with the control elements of said first and second switching means and having a longitudinal axis arranged parallel to the longitudinal axis of said trench, second and third electrically conductive lines disposed on said major surface of said semiconductor substrate in contact with said current carrying electrode of said first and second switching means, respectively, and each having a longitudinal axis arranged orthogonal to the longitudinal axis of said trench, third and fourth .Iadd.spaced apart .Iaddend.storage means disposed .Iadd.solely .Iaddend.on said second sidewall .Iadd.of said trench, .Iaddend. third and fourth .Iadd.spaced apart .Iaddend.switching means, each having a control element .Iadd.disposed solely on said second sidewall of said trench .Iaddend.and a current carrying element, .[.disposed on said second sidewall.]..Iadd.said third and fourth switching means being separated by a portion of said second sidewall of said trench which provides an isolation function, said third and fourth switching means being arranged between said third and fourth storage means, respectively, and said major surface of said substrate and coupled to said respective storage means, and a fourth electrically conductive line disposed on said .Iadd.portion of said .Iaddend.second sidewall .Iadd.of said trench between said third and fourth switching means which provides an isolation function .Iaddend.in contact with the control elements of said third and fourth switching means and having a longitudinal axis arranged parallel to the longitudinal axis of said trench, said second and third electrically conductive lines being connected to the current carrying elements of said third and fourth switching means, respectively.

Claim 27

A memory comprising a semiconductor substrate having a major surface and a trench disposed therein having first and second opposing sidewalls and a longitudinal axis, first and second .Iadd.spaced apart .Iaddend.storage means disposed .Iadd.solely .Iaddend.on a first sidewall of said trench, first and second .Iadd.spaced apart .Iaddend.switching means each having a control element .Iadd.disposed solely on said first sidewall of said trench .Iaddend.and a current carrying element, .[.disposed on said first sidewall of said trench.]. .Iadd.said first and second switching means being separated by a portion of said first sidewall of said trench which provides an isolation function, said first and second switching means being arranged .Iaddend.between said first and second storage means, respectively, and said major surface of said substrate and coupled to said respective storage means, .Iadd.each of said first and second spaced apart switching means being completely formed within a surface area no greater than approximately two lithographic squares, .Iaddend. a first electrically conductive line disposed .[.on.]. .Iadd.solely along .Iaddend.said first sidewall .Iadd.of said trench between said first and second switching means .Iaddend.in contact with the control elements of said first and second switching means and having a longitudinal axis arranged parallel to the longitudinal axis of said trench, second and third electrically conductive lines disposed on said major surface of said semiconductor substrate in contact with said current carrying electrode of said first and second switching means, respectively, and each having a longitudinal axis arranged orthogonal to the longitudinal axis of said trench, third and fourth .Iadd.spaced apart .Iaddend.storage means disposed .Iadd.solely .Iaddend.on said second sidewall .Iadd.of said trench, .Iaddend. third and fourth .Iadd.spaced apart .Iaddend.switching means, each having a control element .Iadd.disposed solely on said second sidewall of said trench .Iaddend.and a current carrying element, .[.disposed on said second sidewall.]..Iadd.said third and fourth switching means being separated by a portion of said second sidewall of said trench which provides an isolation function, said third and fourth switching means being arranged between said third and fourth storage means, respectively, and said major surface of said substrate and coupled to said respective storage means, and a fourth electrically conductive line disposed on said .Iadd.portion of said .Iaddend.second sidewall .Iadd.of said trench between said third and fourth switching means which provides an isolation function .Iaddend.in contact with the control elements of said third and fourth switching means and having a longitudinal axis arranged parallel to the longitudinal axis of said trench, said second and third electrically conductive lines being connected to the current carrying elements of said third and fourth switching means, respectively.

Claim 28

A memory as set forth in claim 20 wherein each of said storage means is a capacitor having a diffusion region in said substrate and a conductive plate insulated from said sidewalls.

Claim 29

A memory as set forth in claim 21 wherein the diffusion regions of said first and second capacitors and the diffusion regions of said third and fourth capacitors are separated by first and second layers of insulation, respectively.

Claim 30

A memory as set forth in claim 22 wherein said conductive plate and said first and fourth conductive lines include doped polysilicon and said second and third lines include aluminum. .Iadd.

Claim 31

A plurality of dynamic random access memory cells, comprising: a semiconductor substrate having a major surface and a plurality of parallel trenches each having a longitudinal axis formed therein, first and second spaced apart storage capacitors disposed solely along a first sidewall of a first said trench, first and second spaced apart bit/sense diffusion regions disposed at the surface of said substrate abutting said first sidewall of said first trench, a first word line disposed solely along said first sidewall of said first trench along the longitudinal axis thereof and insulated from said first sidewall of said first trench, arranged between said first and second spaced apart storage capacitors and said first and second spaced apart bit/sense diffusion regions, respectively, third and fourth spaced apart storage capacitors disposed solely along a second sidewall of a second trench adjacent to said first sidewall of said first trench, a second word line disposed solely along said second sidewall of said second trench along the longitudinal axis thereof and insulated from said second sidewall of said second trench, arranged between said third and fourth spaced apart storage capacitors and said first and second spaced apart bit/sense diffusion regions, respectively, said first and second bit/sense diffusion regions abutting said second sidewall of said second trench, said first storage capacitor, said first bit/sense diffusion region, and said first capacitor defining a first memory cell, said second storage capacitor, said second bit/sense diffusion region, and said first word line defining a second memory cell, said third storage capacitor, said first bit/sense diffusion region, and said second word line defining a third memory cell, and said fourth storage capacitor, said second bit/sense diffusion region, and said second word line defining a fourth memory cell, each of said memory cells being completely formed within a surface area no greater than two lithographic squares. .Iaddend. .Iadd.25. The plurality of dynamic random access memory cells of claim 24, wherein a first isolation means is disposed on said first sidewall of said first trench between said first and second memory cells, and wherein a second isolation means is disposed on said second sidewall of said second trench between said third and fourth memory cells. .Iaddend. .Iadd.26. The plurality of dynamic random access memory cells of claim 25, wherein each of said first and second isolation means comprise thick insulation layers. .Iaddend. .Iadd.27. A memory comprising a semiconductor substrate having a major surface and a trench disposed therein having a longitudinal axis, storage means disposed solely on a given sidewall of said trench, switching means having a control element disposed solely on said given sidewall of said trench and a current carrying element disposed on said given sidewall of said trench between said storage means and said major surface of said substrate and coupled to said storage means, said storage means and said switching means being completely formed within a surface area no greater than approximately two lithographic squares, a first electrically conductive line disposed solely on said given sidewall in contact with said control element of said switching means and having a longitudinal axis arranged parallel to the longitudinal axis of said trench, a second electrically conductive line disposed on said major surface of said semiconductor substrate in contact with said current carrying element of said switching means and having a longitudinal axis arranged orthogonal to the longitudinal axis of said trench, and isolation means disposed on said given sidewall of said trench on either side of said switching means, portions of said first electrically conductive line being disposed on each of said isolation means. .Iaddend.

Claim 32

.Iadd.28. The memory of claim 27, wherein said isolation means comprise a thick insulation layer.