US9425099B2
Active / In Force
US
⏱️ 7.2 years remaining
Epitaxial channel with a counter-halo implant to improve analog gain
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
•
Filing: 2014-01-16
•
Granted: 2016-08-23
•
Expires: 2034-01-16
Abstract
Abstract Some embodiments of the present disclosure relate to an implant that improves long-channel transistor performance with little to no impact on short-channel transistor performance. To mitigate DIBL, both long-channel and short-channel transistors on a substrate are subjected to a halo implant. While the halo implant improves short-channel transistor performance, it degrades long-channel transistor performance. Therefore, a counter-halo implant is performed on the long-channel transistors only to restore their performance. To achieve this, the counter-halo implant is performed at an angle that introduces dopant impurities near the source/drain regions of the long-channel transistors to counteract the effects of the halo implant, while the counter-halo implant is simultaneously shadowed from reaching the channel of the short-channel transistors.
Inventors
- 👤 Tsung-Hsing Yu
- 👤 Shih-Syuan Huang
- 👤 Ken-Ichi Goto
- 👤 Yi-Ming Sheu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 10:17
CPC Classifications
H01L21/823412; H; H10; H10D; H10D30/00; H10D30/60; H10D30/751; H01L21/26586; H01L21/823425; H01L27/088; H01L29/1054; H01L29/1083; H01L29/165; H01L29/66492; H01L29/6659; H01L29/7833; H10D30/01; H10D30/021; H10D30/022; H10D30/0223; H10D30/0227; H10D30/601; H10D62/00; H10D62/10; H10D62/17; H10D62/351; H10D62/357; H10D62/364; H10D62/371; H10D62/80; H10D62/82; H10D62/822; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0128; H10D84/013; H10D84/0133; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/82; H10D84/83; H10P; H10P30/00; H10P30/20; H10P30/22; H10P30/221; H10P30/222; H01L21/2658; H10P30/225
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
188 words
A method, comprising: forming a plurality of first gate structures over a substrate, wherein the plurality of first gate structures have a vertical dimension (h) and are separated by a first horizontal space (s 1 ); forming a plurality of second gate structures on the substrate, wherein the plurality of second gate structures have the vertical dimension (h) and are separated by a second horizontal space (s 2 ), which is greater than the first horizontal space (s 1 ); performing a first implant at a first angle with a vertical line to form halo regions within the substrate, wherein the halo regions extend below the plurality of first gate structures and the plurality of second gate structures; and performing a second implant after the first implant and at a second angle with the vertical line to introduce dopant impurities into the substrate that reduce a doping concentration of the halo regions that extend below the plurality of second structures, wherein the second angle is greater than the first angle such that the second implant is blocked from reaching the substrate by the plurality of first gate structures.
Claim 2
Independent Claim
188 words
A method, comprising: forming a plurality of first gate structures over a substrate, wherein the plurality of first gate structures have a vertical dimension (h) and are separated by a first horizontal space (s 1 ); forming a plurality of second gate structures on the substrate, wherein the plurality of second gate structures have the vertical dimension (h) and are separated by a second horizontal space (s 2 ), which is greater than the first horizontal space (s 1 ); performing a first implant at a first angle with a vertical line to form halo regions within the substrate, wherein the halo regions extend below the plurality of first gate structures and the plurality of second gate structures; and performing a second implant after the first implant and at a second angle with the vertical line to introduce dopant impurities into the substrate that reduce a doping concentration of the halo regions that extend below the plurality of second structures, wherein the second angle is greater than the first angle such that the second implant is blocked from reaching the substrate by the plurality of first gate structures.
Claim 3
Dependent Claim
33 words
The method of claim 1 , further comprising: forming an epitaxial layer over the substrate; forming the plurality of first gate structures and the plurality of second gate structures over the epitaxial layer.
Claim 4
Dependent Claim
27 words
The method of claim 2 , further comprising: forming a carbon-containing epitaxial layer over the substrate, wherein the epitaxial layer is formed over the carbon-containing epitaxial layer.
Claim 5
Dependent Claim
26 words
The method of claim 1 , further comprising: performing a third implant, after performing the second implant, to form source and drain regions within the substrate.
Claim 6
Independent Claim
259 words
A method, comprising: introducing dopant impurities of a first impurity type into first and second transistor regions of a substrate, wherein the first and second transistor regions comprise first and second channel regions and first and second source/drain regions, respectively; recessing the substrate over the first and second transistor regions; forming first and second layers of carbon-containing material over the first and second transistor regions; forming first and second layers of substrate material over the first and second layers of carbon-containing material; forming first and second gate dielectrics over the first and second layers of substrate material; forming first and second gate structures over the first and second gate dielectrics in the first and second channel regions, wherein the first gate structure is separated by a first horizontal space (s 1 ) from a third gate structure, and wherein the second gate structure is separated by a second horizontal space (s 2 ) from a fourth gate structure, and wherein s 2 is greater than s 1 ; performing a first implant at a first angle with a vertical line to introduce further dopant impurities of the first impurity type into the substrate at edges of the first and second channel regions; and performing a second implant at a second angle with the vertical line to introduce dopant impurities of a second impurity type, which is opposite the first impurity type, wherein the second angle is greater than a first threshold such that the second implant is blocked from reaching the first channel region by the third gate structure.
Claim 7
Independent Claim
259 words
A method, comprising: introducing dopant impurities of a first impurity type into first and second transistor regions of a substrate, wherein the first and second transistor regions comprise first and second channel regions and first and second source/drain regions, respectively; recessing the substrate over the first and second transistor regions; forming first and second layers of carbon-containing material over the first and second transistor regions; forming first and second layers of substrate material over the first and second layers of carbon-containing material; forming first and second gate dielectrics over the first and second layers of substrate material; forming first and second gate structures over the first and second gate dielectrics in the first and second channel regions, wherein the first gate structure is separated by a first horizontal space (s 1 ) from a third gate structure, and wherein the second gate structure is separated by a second horizontal space (s 2 ) from a fourth gate structure, and wherein s 2 is greater than s 1 ; performing a first implant at a first angle with a vertical line to introduce further dopant impurities of the first impurity type into the substrate at edges of the first and second channel regions; and performing a second implant at a second angle with the vertical line to introduce dopant impurities of a second impurity type, which is opposite the first impurity type, wherein the second angle is greater than a first threshold such that the second implant is blocked from reaching the first channel region by the third gate structure.
Claim 8
Dependent Claim
35 words
The method of claim 5 , wherein the second angle is less than a second threshold such that the second implant is not blocked from reaching the second channel region by the fourth gate structure.
Claim 9
Dependent Claim
20 words
The method of claim 6 , wherein the first, second, third, and fourth gate structures have a vertical dimension (h).
Claim 10
Dependent Claim
17 words
The method of claim 7 , wherein the second threshold is about equal to arctangent(s 2 /h).
Claim 11
Dependent Claim
17 words
The method of claim 7 , wherein the first threshold is about equal to arctangent(s 1 /h).
Claim 12
Dependent Claim
15 words
The method of claim 5 , wherein the first and second implants comprise ion implants.
Claim 13
Dependent Claim
22 words
The method of claim 5 , wherein the dopant impurities of the first impurity type comprise boron, carbon, indium, or combinations thereof.
Claim 14
Dependent Claim
22 words
The method of claim 5 , wherein the dopant impurities of the second impurity type comprise phosphorous, antimony, arsenic, or combinations thereof.
Claim 15
Dependent Claim
22 words
The method of claim 5 , where the first impurity type comprises n-type and the second impurity type comprises p-type, or vice-versa.
Claim 16
Dependent Claim
31 words
The method of claim 5 , further comprising performing an anneal after introducing the dopant impurities of the first impurity type into the first and second transistor regions of the substrate.
Claim 17
Dependent Claim
21 words
The method of claim 5 , wherein first and second gate structures comprise a hard mask disposed above a gate electrode.
Claim 18
Dependent Claim
19 words
The method of claim 5 , wherein the substrate material comprises silicon and the carbon-containing material comprises silicon carbide.
Claim 19
Dependent Claim
112 words
The method of claim 5 , further comprising: performing a third implant to introduce first additional dopant impurities into the first and second channel regions, wherein the third implant enhances source-to-drain current control within the first channel region but increases a threshold voltage within the second channel region by a delta value; and performing a fourth implant at the second angle with the vertical line to introduce second additional dopant impurities into the second channel region while blocking the second additional dopant impurities from reaching the first channel region by the third gate structure, wherein the fourth implant reduces the threshold voltage within the second channel region by about the delta value.
Claim 20
Independent Claim
176 words
A method comprising: performing a well implant to introduce dopant impurities of a first impurity type into first and second transistor regions of a substrate; forming an epitaxial layer comprising carbon over the substrate; forming a plurality of first gate structures and a plurality of second gate structures over the epitaxial layer, respectively on the first and second transistor regions, wherein the plurality of first gate structures are separated by a first horizontal space (s 1 ), wherein the plurality of second gate structures are separated by a second horizontal space (s 2 ), which is greater than s 1 , and wherein the plurality of first and second gate structures share a common height (h); and performing a counter-halo implant to introduce dopant impurities of a second impurity type, opposite the first impurity type, into the second transistor region, wherein the counter-halo implant is performed at a first angle with respect to a vertical line in which the counter-halo implant is blocked from reaching the first transistor region by the plurality of first gate structures.
Claim 21
Independent Claim
176 words
A method comprising: performing a well implant to introduce dopant impurities of a first impurity type into first and second transistor regions of a substrate; forming an epitaxial layer comprising carbon over the substrate; forming a plurality of first gate structures and a plurality of second gate structures over the epitaxial layer, respectively on the first and second transistor regions, wherein the plurality of first gate structures are separated by a first horizontal space (s 1 ), wherein the plurality of second gate structures are separated by a second horizontal space (s 2 ), which is greater than s 1 , and wherein the plurality of first and second gate structures share a common height (h); and performing a counter-halo implant to introduce dopant impurities of a second impurity type, opposite the first impurity type, into the second transistor region, wherein the counter-halo implant is performed at a first angle with respect to a vertical line in which the counter-halo implant is blocked from reaching the first transistor region by the plurality of first gate structures.
Claim 22
Dependent Claim
24 words
The method of claim 18 , wherein the first angle is greater than approximately arctangent(s 1 /h) and less than approximately arctangent(s 2 /h).
Claim 23
Dependent Claim
64 words
The method of claim 18 , further comprising: performing a halo implant to introduce dopant impurities of the first impurity type into regions of the first and second transistor regions unmasked by both the plurality of first and second gate structures, wherein the halo implant is performed at a second angle with respect to the vertical line that is less than the first angle.
References Cited (Backward Citations)
US5355006A
Cited
US5561302A
Cited
US6040208A
Cited
US6215148B1
Cited
US6541343B1
Cited
US6566204B1
Cited
US6589847B1
Cited
US20020033511A1
Cited
US20030008484A1
Cited
US20050023535A1
Cited
US20030075719A1
Cited
US7507999B2
Cited
US20050173739A1
Cited
US6849890B2
Cited
US20050285212A1
Cited
US7276407B2
Cited
US20060065937A1
Cited
US20060220098A1
Cited
US7952149B2
Cited
US8034679B1
Cited
US20070190731A1
Cited
US20080195983A1
Cited
US20080242032A1
Cited
US20080272395A1
Cited
US7943468B2
Cited
US8404546B2
Cited
US20090289280A1
Cited
KR20100080159A
Cited
US20100317169A1
Cited
US20100330763A1
Cited
US20110031503A1
Cited
US20110079861A1
Cited
US20110215376A1
Cited
US8557659B2
Cited
US8659054B2
Cited
US20120135575A1
Cited
US8569156B1
Cited
US8298895B1
Cited
US20130113041A1
Cited
US20130200455A1
Cited
TW201349304A
Cited
US8669615B1
Cited
US20140197411A1
Cited
US20140252504A1
Cited
US9224814B2
Cited
US20150243759A1
Cited
US20150263092A1
Cited
US20150295085A1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2019-08-23 | 2020-02-22 | 2020-08-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2023-08-23 | 2024-02-22 | 2024-08-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2027-08-23 | 2028-02-22 | 2028-08-23 | $7700.00 | Pending Window |