US8659054B2
Active / In Force
US
⏱️ 4.0 years remaining
Method and structure for pFET junction profile with SiGe channel
Assignee: GlobalFoundries US Inc
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Filing: 2010-10-15
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Granted: 2014-02-25
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Expires: 2030-10-15
Abstract
Abstract A semiconductor structure including a p-channel field effect transistor (pFET) device located on a surface of a silicon germanium (SiGe) channel is provided in which the junction profile of the source region and the drain region is abrupt. The abrupt source/drain junctions for pFET devices are provided in this disclosure by forming an N- or C-doped Si layer directly beneath a SiGe channel layer which is located above a Si substrate. A structure is thus provided in which the N- or C-doped Si layer (sandwiched between the SiGe channel layer and the Si substrate) has approximately the same diffusion rate for a p-type dopant as the overlying SiGe channel layer. Since the N- or C-doped Si layer and the overlying SiGe channel layer have substantially the same diffusivity for a p-type dopant and because the N- or C-doped Si layer retards diffusion of the p-type dopant into the underlying Si substrate, abrupt source/drain junctions can be formed.
Inventors
- 👤 Kern Rim
- 👤 William K. Henson
- 👤 Yue Liang
- 👤 Xinlin Wang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 12:36
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H10P; H10P30/00; H10P30/20; H10P30/202; H10P30/204; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D30/60; H10D30/751; H10D62/17; H10D62/351; H10D62/357; H10D62/364; H10D62/371; H10P30/208; H10P30/222; H10D30/791; H10D30/798
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
137 words
A method of fabricating a semiconductor structure comprising: providing a structure including a Si substrate, an N- or C-doped Si layer located on an upper surface of the Si substrate, and a SiGe channel layer located on an upper surface of the N- or C-doped Si layer; forming a p-FET gate stack directly on an upper surface of the SiGe channel layer; and forming a source region and a drain region into a portion of the SiGe channel layer, a portion of the N- or C-doped Si layer and at a footprint of the pFET gate stack by ion implantation of a p-type dopant, wherein said source region and said drain region have an abrupt junction profile and wherein a bottom surface portion of each of said source region and said drain region contacts the Si substrate.
Claim 2
Independent Claim
137 words
A method of fabricating a semiconductor structure comprising: providing a structure including a Si substrate, an N- or C-doped Si layer located on an upper surface of the Si substrate, and a SiGe channel layer located on an upper surface of the N- or C-doped Si layer; forming a p-FET gate stack directly on an upper surface of the SiGe channel layer; and forming a source region and a drain region into a portion of the SiGe channel layer, a portion of the N- or C-doped Si layer and at a footprint of the pFET gate stack by ion implantation of a p-type dopant, wherein said source region and said drain region have an abrupt junction profile and wherein a bottom surface portion of each of said source region and said drain region contacts the Si substrate.
Claim 3
Dependent Claim
53 words
The method of claim 1 wherein said providing the structure includes forming the SiGe channel layer on an upper surface of the Si substrate and then forming the N- or C-doped layer within an upper portion of the Si substrate by implanting N or C into said upper region of the Si substrate.
Claim 4
Dependent Claim
31 words
The method of claim 1 wherein said forming the SiGe channel layer on the upper surface of the Si substrate comprises an epitaxial growth process and said SiGe layer is strained.
Claim 5
Dependent Claim
35 words
The method of claim 2 wherein said implanting N or C is performed at an energy from 2 keV to 10 keV using an ion dose from 1e12 atoms/cm 2 to 5e15 atoms/cm 2 .
Claim 6
Dependent Claim
44 words
The method of claim 1 wherein said providing the structure includes forming the N- or C-doped Si layer on an upper surface of the Si substrate, and then forming the SiGe channel layer on an upper surface of the N- or C-doped Si layer.
Claim 7
Dependent Claim
26 words
The method of claim 5 wherein said forming the N- or C-doped Si layer and forming the SiGe channel layer both include an epitaxial growth process.
Claim 8
Dependent Claim
23 words
The method of claim 6 wherein vacuum is maintained during forming the N- or C-doped Si layer and forming the SiGe channel layer.
Claim 9
Dependent Claim
44 words
The method of claim 1 wherein said providing the structure includes forming the N- or C-doped Si layer within an upper region of the Si substrate, and then forming the SiGe channel layer on an upper surface of the N- or C-doped Si layer.
Claim 10
Dependent Claim
28 words
The method of claim 8 wherein said forming the N- or C-doped Si layer includes ion implanting N or C into the upper region of the Si substrate.
Claim 11
Dependent Claim
35 words
The method of claim 9 wherein said implanting N or C is performed at an energy from 2 keV to 10 keV using an ion dose from 1e12 atoms/cm 2 to 5e15 atoms/cm 2 .
Claim 12
Dependent Claim
16 words
The method of claim 8 wherein forming the SiGe channel layer comprises an epitaxial growth process.
Claim 13
Dependent Claim
119 words
A semiconductor structure comprising: a Si substrate, a N- or C-doped Si layer located on an upper surface of the Si substrate, a SiGe channel layer located on an upper surface of the N- or C-doped Si layer, a pFET gate stack located directly on an upper surface of the SiGe channel layer, and a source region and a drain region, each of which is located within a portion of the SiGe layer, a portion of the N- or C-doped Si layer and at a footprint of the pFET gate stack, and each of which includes an abrupt junction and wherein a bottom surface portion of each of said source region and said drain region contacts the Si substrate.
Claim 14
Dependent Claim
119 words
A semiconductor structure comprising: a Si substrate, a N- or C-doped Si layer located on an upper surface of the Si substrate, a SiGe channel layer located on an upper surface of the N- or C-doped Si layer, a pFET gate stack located directly on an upper surface of the SiGe channel layer, and a source region and a drain region, each of which is located within a portion of the SiGe layer, a portion of the N- or C-doped Si layer and at a footprint of the pFET gate stack, and each of which includes an abrupt junction and wherein a bottom surface portion of each of said source region and said drain region contacts the Si substrate.
Claim 15
Dependent Claim
21 words
The semiconductor structure of claim 12 wherein said N- or C-doped Si layer is an epitaxial N- or C-doped Si layer.
Claim 16
Dependent Claim
17 words
The semiconductor structure of claim 12 wherein said SiGe channel layer is an epitaxial SiGe channel layer.
Claim 17
Dependent Claim
13 words
The semiconductor structure of claim 12 wherein said SiGe channel layer is strained.
Claim 18
Dependent Claim
15 words
The semiconductor structure of claim 12 wherein said N- or C-doped Si layer comprises Si:N.
Claim 19
Dependent Claim
15 words
The semiconductor structure of claim 12 wherein said N- or C-doped Si layer comprises Si:C.
Claim 20
Dependent Claim
21 words
The semiconductor structure of claim 12 wherein said N- or C-doped Si layer is continuously present beneath the SiGe channel layer.
Claim 21
Dependent Claim
19 words
The semiconductor structure of claim 12 wherein said N- or C-doped layer is partially present beneath the SiGe layer.
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