US9224814B2
Active / In Force
US
⏱️ 7.2 years remaining
Process design to improve transistor variations and performance
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
•
Filing: 2014-01-16
•
Granted: 2015-12-29
•
Expires: 2034-01-16
Abstract
Abstract The present disclosure relates to a method of forming a transistor device having a carbon implantation region that provides for a low variation of voltage threshold, and an associated apparatus. The method is performed by forming a well region within a semiconductor substrate. The semiconductor substrate is selectively etched to form a recess within the well region. After formation of the recess, a carbon implantation is selectively performed to form a carbon implantation region within the semiconductor substrate at a position underlying the recess. An epitaxial growth is then performed to form one or more epitaxial layers within the recess at a position overlying the carbon implantation region. Source and drain regions are subsequently formed within the semiconductor substrate such that a channel region, comprising the one or more epitaxial layers, separates the source/drains from one another.
Inventors
- 👤 Tsung-Hsing Yu
- 👤 Chia-Wen Liu
- 👤 Yeh Hsu
- 👤 Shih-Syuan Huang
- 👤 Ken-Ichi Goto
- 👤 Zhiqiang Wu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 12:38
CPC Classifications
H01L29/0847; H; H10; H10D; H10D30/00; H10D30/60; H10D30/601; H10D30/605; H01L21/02238; H01L21/02532; H01L21/02636; H01L21/26506; H01L21/30604; H01L29/16; H01L29/66545; H01L29/6659; H01L29/7836; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D30/751; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H10D62/17; H10D62/351; H10D62/357; H10D62/364; H10D62/371; H10D62/80; H10D62/83; H10D62/832; H10D64/00; H10D64/01; H10D64/017; H10P; H10P14/00; H10P14/20; H10P14/27; H10P14/34; H10P14/3402; H10P14/3404; H10P14/3411; H10P14/60; H10P14/63; H10P14/6302; H10P14/6304; H10P14/6306; H10P14/6308; H10P14/6309; H10P14/6322; H10P30/00; H10P30/20; H10P30/202; H10P30/204; H10P30/208; H10P50/00; H10P50/60; H10P50/64; H10P50/642; H10P30/222
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
188 words
A method of forming a transistor device, comprising: forming a well region within a semiconductor substrate; selectively etching the semiconductor substrate to form a recess within the well region along a top surface of the semiconductor substrate; selectively performing a carbon implantation within the recess to form a carbon implantation region within the semiconductor substrate at a position underlying the recess; performing an epitaxial growth process to form one or more epitaxial layers within the recess at positions overlying the carbon implantation region, wherein the one or more epitaxial layers comprise a carbon doped silicon epitaxial layer and a silicon epitaxial layer disposed onto the carbon doped silicon epitaxial layer; forming a gate structure onto the silicon epitaxial layer, wherein the gate structure comprises a gate dielectric layer disposed onto the silicon epitaxial layer and a gate electrode layer disposed onto the gate dielectric layer; and forming a source region and a drain region on opposing sides of the gate structure, such that a channel region comprising the one or more epitaxial layers, which is arranged under the gate structure, separates the source region from the drain region.
Claim 2
Independent Claim
188 words
A method of forming a transistor device, comprising: forming a well region within a semiconductor substrate; selectively etching the semiconductor substrate to form a recess within the well region along a top surface of the semiconductor substrate; selectively performing a carbon implantation within the recess to form a carbon implantation region within the semiconductor substrate at a position underlying the recess; performing an epitaxial growth process to form one or more epitaxial layers within the recess at positions overlying the carbon implantation region, wherein the one or more epitaxial layers comprise a carbon doped silicon epitaxial layer and a silicon epitaxial layer disposed onto the carbon doped silicon epitaxial layer; forming a gate structure onto the silicon epitaxial layer, wherein the gate structure comprises a gate dielectric layer disposed onto the silicon epitaxial layer and a gate electrode layer disposed onto the gate dielectric layer; and forming a source region and a drain region on opposing sides of the gate structure, such that a channel region comprising the one or more epitaxial layers, which is arranged under the gate structure, separates the source region from the drain region.
Claim 3
Dependent Claim
30 words
The method of claim 1 , wherein the carbon implantation region is configured to mitigate back diffusion of dopants from the well region to the one or more epitaxial layers.
Claim 4
Dependent Claim
42 words
The method of claim 1 , further comprising: performing an oxidation process to form a layer of dielectric material over the one or more epitaxial layers, wherein the oxidation process comprises a maximum temperature of less than or equal to 950° C.
Claim 5
Dependent Claim
25 words
The method of claim 3 , further comprising: removing the layer of dielectric material prior to forming the gate structure onto the silicon epitaxial layer.
Claim 6
Dependent Claim
39 words
The method of claim 1 , wherein a doping concentration profile within the channel region has a concentration that is less than 1 e18 cm −3 at an interface between the silicon epitaxial layer and the gate dielectric layer.
Claim 7
Dependent Claim
36 words
The method of claim 5 , wherein a carbon doping profile has a peak concentration at a depth of between approximately 10 nm and approximately 15 nm below an upper surface of the silicon epitaxial layer.
Claim 8
Dependent Claim
78 words
The method of claim 1 , wherein forming the gate structure comprises: forming a dummy gate structure onto the silicon epitaxial layer; removing the dummy gate structure after forming the source region and the drain region; depositing an inter-layer gate dielectric layer or a high-k gate dielectric layer into a position of the removed dummy gate structure; and depositing a metal replacement gate electrode onto the inter-layer gate dielectric layer or the high-k gate dielectric layer dielectric layer.
Claim 9
Dependent Claim
24 words
The method of claim 1 , wherein the carbon implantation is performed with an implantation energy that is less than 5 kiloelectron volts (keV).
Claim 10
Dependent Claim
23 words
The method of claim 1 , wherein the carbon implantation region extends below lower surfaces of the source region and the drain region.
Claim 11
Dependent Claim
33 words
The method of claim 1 , wherein the carbon implantation region, the carbon doped silicon epitaxial layer, and the silicon epitaxial layer are laterally arranged between the source region and the drain region.
Claim 12
Independent Claim
168 words
A method of forming a transistor device, comprising: forming a well region within a semiconductor substrate; selectively etching the semiconductor substrate to form a recess within the well region along a top surface of the semiconductor substrate; selectively performing a carbon implantation within the recess to form a carbon implantation region within the semiconductor substrate at a position underlying the recess; performing an epitaxial growth process to form a carbon doped silicon epitaxial layer within the recess at a position overlying the carbon implantation region and to form a lightly doped silicon epitaxial layer overlying the carbon doped silicon epitaxial layer; forming a replacement metal gate structure over the lightly doped silicon epitaxial layer; and forming a source region and a drain region on opposing sides of the replacement metal gate structure, such that a channel region comprising the carbon doped silicon epitaxial layer and the lightly doped silicon epitaxial layer, which is arranged under the replacement metal gate structure, separates the source region from the drain region.
Claim 13
Independent Claim
168 words
A method of forming a transistor device, comprising: forming a well region within a semiconductor substrate; selectively etching the semiconductor substrate to form a recess within the well region along a top surface of the semiconductor substrate; selectively performing a carbon implantation within the recess to form a carbon implantation region within the semiconductor substrate at a position underlying the recess; performing an epitaxial growth process to form a carbon doped silicon epitaxial layer within the recess at a position overlying the carbon implantation region and to form a lightly doped silicon epitaxial layer overlying the carbon doped silicon epitaxial layer; forming a replacement metal gate structure over the lightly doped silicon epitaxial layer; and forming a source region and a drain region on opposing sides of the replacement metal gate structure, such that a channel region comprising the carbon doped silicon epitaxial layer and the lightly doped silicon epitaxial layer, which is arranged under the replacement metal gate structure, separates the source region from the drain region.
Claim 14
Dependent Claim
37 words
The method of claim 11 , wherein the carbon implantation region is configured to mitigate back diffusion of dopants from the well region to the carbon doped silicon epitaxial layer and the lightly doped silicon epitaxial layer.
Claim 15
Dependent Claim
43 words
The method of claim 12 , wherein a doping concentration profile within the channel region has a concentration that is less than 1 el 8 cm −3 at an interface between the lightly doped silicon epitaxial layer and the replacement metal gate structure.
Claim 16
Dependent Claim
82 words
The method of claim 12 , wherein forming the replacement metal gate structure comprises: forming a dummy gate structure onto the lightly doped silicon epitaxial layer; removing the dummy gate structure after forming the source region and the drain region; depositing an inter-layer gate dielectric layer or a high-k gate dielectric layer into a position of the removed dummy gate structure; and depositing a metal replacement gate electrode onto the inter-layer gate dielectric layer or the high-k gate dielectric layer dielectric layer.
Claim 17
Dependent Claim
49 words
The method of claim 11 , further comprising: performing an oxidation process to form a layer of dielectric material over the carbon doped silicon epitaxial layer and the lightly doped silicon epitaxial layer, wherein the oxidation process comprises a maximum temperature of less than or equal to 950° C.
Claim 18
Independent Claim
151 words
A method of forming a transistor device, comprising: selectively etching a semiconductor substrate to form a recess within a well region arranged within an upper surface of the semiconductor substrate; selectively performing a carbon implantation to form a carbon implantation region within the semiconductor substrate at a position underlying the recess; performing an epitaxial growth process to form an epitaxial region having one or more epitaxial layers within the recess at positions overlying the carbon implantation region; forming a source region and a drain region that vertically extend from an upper surface of the epitaxial region to within the carbon implantation region; and wherein the transistor device comprises a carbon doping profile that decreases from the upper surface of the epitaxial region to a first depth within the epitaxial region, that increases from the first depth to a second depth within the semiconductor substrate, and that decreases below the second depth.
Claim 19
Independent Claim
151 words
A method of forming a transistor device, comprising: selectively etching a semiconductor substrate to form a recess within a well region arranged within an upper surface of the semiconductor substrate; selectively performing a carbon implantation to form a carbon implantation region within the semiconductor substrate at a position underlying the recess; performing an epitaxial growth process to form an epitaxial region having one or more epitaxial layers within the recess at positions overlying the carbon implantation region; forming a source region and a drain region that vertically extend from an upper surface of the epitaxial region to within the carbon implantation region; and wherein the transistor device comprises a carbon doping profile that decreases from the upper surface of the epitaxial region to a first depth within the epitaxial region, that increases from the first depth to a second depth within the semiconductor substrate, and that decreases below the second depth.
Claim 20
Dependent Claim
55 words
The method of claim 16 , further comprising: performing an oxidation process to form a layer of dielectric material over the epitaxial region, wherein the oxidation process remains at a maximum temperature of less than or equal to 950° C. for a time in a range of between approximately 10 seconds and approximately 60 seconds.
Claim 21
Dependent Claim
45 words
The method of claim 17 , wherein the oxidation process forms an n-type or p-type doping profile that monotonically decreases from a lower surface of the epitaxial region to a doping concentration of less than 1E18 cm−3 at the upper surface of the epitaxial region.
Claim 22
Dependent Claim
37 words
The method of claim 16 , wherein the one or more epitaxial layers, comprise: a carbon doped epitaxial layer formed onto the carbon implantation region; and a lightly-doped epitaxial layer formed onto the carbon doped epitaxial layer.
Claim 23
Dependent Claim
35 words
The method of claim 16 , wherein the carbon doping profile has a peak concentration at a depth of between approximately 10 nm and approximately 15 nm below the upper surface of the epitaxial region.
References Cited (Backward Citations)
US6541343B1
Cited
US20020033511A1
Cited
US20030075719A1
Cited
US20050023535A1
Cited
US7507999B2
Cited
US20050173739A1
Cited
US20050285212A1
Cited
US20060065937A1
Cited
US20070190731A1
Cited
US20080242032A1
Cited
US8404546B2
Cited
US20090289280A1
Cited
US20110079861A1
Cited
US20110215376A1
Cited
US8659054B2
Cited
US20120135575A1
Cited
US8569156B1
Cited
US20140197411A1
Cited
US20140252504A1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2018-12-28 | 2019-06-29 | 2019-12-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2022-12-28 | 2023-06-29 | 2023-12-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2026-12-28 | 2027-06-29 | 2027-12-29 | $7700.00 | Pending Window |