Patent US7268531B2 successfully refreshed from Google Patents.
US7268531B2
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Apparatus for improving stability and lock time for synchronous circuits
Assignee: Micron Technology Inc
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Filing: 2005-01-03
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Granted: 2007-09-11
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Expires: 2025-01-03
Abstract
Abstract Delay-locked loops, signal locking methods and devices and system incorporating delay-locked loops are described. A delay-locked loop includes a forward delay path, a feedback delay path, a phase detector and a timer circuit. The forward delay path alternatively couples to an external clock signal and to an internal test signal. The phase detector adjusts a delay line based upon the phase differences of a feedback signal and the external clock signal. The timer circuit switches the test signal into the forward delay path and measures the time of traversal of the test signal around the forward delay path and the feedback delay path and generates a time constant for configuring the phase detector's update period. The phase detector is thereafter able to stabilize at an improved rate.
Inventors
- 👤 Feng Lin
- 👤 J. Brian Johnson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 06:03
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/12015; G11C29/02; G11C29/022; G11C29/023; G11C29/028; G11C29/50; G11C29/50012; G11C7/00; G11C7/02; G11C7/10; G11C7/1051; G11C7/106; G11C7/1066; G11C7/22; G11C7/222
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
90 words
A delay-locked loop, comprising: a delay line configured to receive an external clock signal and configured to couple with an output driver of a memory device; an I/O model configured to couple with the delay line and configured to model delay of the output driver; a phase detector coupled to the delay line and differentially responsive to feedback via the I/O model and the external clock; and a timer circuit switchably coupled to the delay line and the timer circuit to generate a test signal for calculating a loop delay.
Claim 2
Dependent Claim
90 words
A delay-locked loop, comprising: a delay line configured to receive an external clock signal and configured to couple with an output driver of a memory device; an I/O model configured to couple with the delay line and configured to model delay of the output driver; a phase detector coupled to the delay line and differentially responsive to feedback via the I/O model and the external clock; and a timer circuit switchably coupled to the delay line and the timer circuit to generate a test signal for calculating a loop delay.
Claim 3
Dependent Claim
31 words
The delay-locked loop of claim 1 , further comprising: a clock input path configured to receive via a clock input path and provide the external clock signal to the delay line.
Claim 4
Dependent Claim
64 words
The delay-locked loop of claim 2 , wherein the clock input path includes a multiplexer having a first input for coupling with the external clock signal and a second input for coupling with the output of the timer circuit, the multiplexer for alternatively switching the external clock signal and the test signal to an output coupled to the first input of the delay line.
Claim 5
Dependent Claim
28 words
The delay-locked loop of claim 2 , wherein the I/O model further comprises a clock input path delay model configured to model delay of the clock input path.
Claim 6
Dependent Claim
30 words
The delay-locked loop of claim 1 , wherein the phase detector is configured to suspend generation of an output signal during calculation of the loop delay by the timer circuit.
Claim 7
Dependent Claim
27 words
The delay-locked loop of claim 1 , wherein the phase detector is configured to generate an output at a period of, at most, once per loop delay.
Claim 8
Dependent Claim
47 words
The delay-locked loop of claim 1 , wherein the delay line is configured with a first delay path for inserting a delay during an initialization mode of the phase detector and a second delay path for inserting a delay during an operational mode of the delay-locked loop.
Claim 9
Dependent Claim
19 words
The delay-locked loop of claim 7 , wherein the first delay path is configured as a synchronous mirror delay.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2010-09-10 | 2011-03-12 | 2011-09-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2014-09-10 | 2015-03-12 | 2015-09-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2018-09-10 | 2019-03-12 | 2019-09-11 | $7700.00 | Window Closed / Lapsed |