Patent US6842399B2 successfully refreshed from Google Patents.
US6842399B2
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US
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Delay lock loop circuit useful in a synchronous system and associated methods
Assignee: Round Rock Research LLC
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Filing: 2003-11-12
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Granted: 2005-01-11
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Expires: 2023-11-12
Abstract
Abstract A method and circuitry for a delay lock loop useful in synchronizing the accessing of a memory array with a system clock is disclosed. In a preferred embodiment, the delay lock loop includes a variable delay element. The delay of the variable delay element is initially set to a minimum delay value. The system clock is then frequency divided and sent to the variable delay element, the output of which will ultimately be used to access the memory array in a synchronized manner with the system clock. The frequency divided clock and the output of the variable delay element are input to a phase detector, which creates a control signal for adjusting the delay of the variable delay element. After the signals are determined to be locked by the phase detector, an undivided clock signal version of the clock signal is sent to the variable delay element, and a frequency divided version of the output of the variable delay element is sent to the phase detector in lieu of the previous output of the variable delay element.
Inventors
- 👤 Ronnie M. Harrison
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 05:16
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/18; H; H03; H03K; H03K23/00; H03K23/40; H03K23/50; H03K23/54; H03K23/542; H03K23/64; H03K23/66; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/081; H03L7/0812; H03L7/0816; H03L7/085; H03L7/089; H03L7/0891; H03L7/0895; H03L7/0896; H03L7/095; H03L2207/00; H03L2207/18
Claims Analysis
Total Claims: 79
Claim 1
Independent Claim
85 words
A method of synchronizing a clock signal using a delay lock loop, comprising: initially fixing a control signal to a reset value; frequency dividing the clock signal to provide a divided signal; coupling the divided signal to an input of a variable delay circuit, the variable delay circuit outputting a delayed signal; comparing the divided signal to a phase of the delayed signal to modify the initially fixed control signal; and applying the modified control signal to the variable delay circuit to control its delay.
Claim 2
Independent Claim
85 words
A method of synchronizing a clock signal using a delay lock loop, comprising: initially fixing a control signal to a reset value; frequency dividing the clock signal to provide a divided signal; coupling the divided signal to an input of a variable delay circuit, the variable delay circuit outputting a delayed signal; comparing the divided signal to a phase of the delayed signal to modify the initially fixed control signal; and applying the modified control signal to the variable delay circuit to control its delay.
Claim 3
Dependent Claim
19 words
The method of claim 1 , wherein the reset value sets the variable delay circuit to a minimum setting.
Claim 4
Dependent Claim
15 words
The method of claim 1 , wherein the variable delay circuit includes a propagation delay.
Claim 5
Dependent Claim
15 words
The method of claim 1 , wherein the control signal comprises use of an integrator.
Claim 6
Dependent Claim
16 words
The method of claim 1 , wherein the control signal comprises use of a charge pump.
Claim 7
Dependent Claim
36 words
The method of claim 1 , wherein comparing the divided signal to a phase of the delayed signal to generate a control signal involves assessing the phase difference between the divided signal and the delayed signal.
Claim 8
Dependent Claim
30 words
The method of claim 1 , wherein the method produces the delayed signal such that it is synchronized with reading or writing of data to and from a memory array.
Claim 9
Dependent Claim
25 words
The method of claim 7 , further comprising coupling the delayed signal to a vernier circuit to produce various delayed representations of the delayed signal.
Claim 10
Dependent Claim
20 words
The method of claim 8 , further comprising selecting one of the delayed representations to synchronize the reading and writing.
Claim 11
Dependent Claim
13 words
The method of claim 9 , wherein selecting is accomplished by a multiplexer.
Claim 12
Independent Claim
92 words
A method of locking a delay lock loop in synchronization with a clock signal, comprising: initializing a variable delay circuit within the delay lock loop to a minimum delay value, wherein the output of the variable delay circuit is coupled to a feedback loop, and wherein delay of the variable delay circuit is controlled by a control signal generated by the feedback loop; frequency dividing the clock signal and inputting it into the variable delay circuit; and locking the frequency-divided clock signal by adjusting the control signal to the variable delay circuit.
Claim 13
Independent Claim
92 words
A method of locking a delay lock loop in synchronization with a clock signal, comprising: initializing a variable delay circuit within the delay lock loop to a minimum delay value, wherein the output of the variable delay circuit is coupled to a feedback loop, and wherein delay of the variable delay circuit is controlled by a control signal generated by the feedback loop; frequency dividing the clock signal and inputting it into the variable delay circuit; and locking the frequency-divided clock signal by adjusting the control signal to the variable delay circuit.
Claim 14
Dependent Claim
18 words
The method of claim 11 , further comprising coupling a frequency divider into the feedback loop after locking.
Claim 15
Dependent Claim
15 words
The method of claim 11 , wherein the variable delay circuit includes a propagation delay.
Claim 16
Dependent Claim
31 words
The method of claim 11 , wherein the feedback loop comprises a phase detector for comparing the phase difference between the clock signal and the output of the variable delay circuit.
Claim 17
Dependent Claim
20 words
The method of claim 14 , further comprising an integrator coupled to the phase detector for producing the control signal.
Claim 18
Dependent Claim
28 words
The method of claim 11 , wherein the output of the variable delay circuit is synchronized with reading or writing of data to and from a memory array.
Claim 19
Dependent Claim
25 words
The method of claim 16 , further comprising coupling the delayed signal to a vernier circuit to produce various delayed representations of the delayed signal.
Claim 20
Dependent Claim
20 words
The method of claim 17 , further comprising selecting one of the delayed representations to synchronize the reading and writing.
Claim 21
Dependent Claim
13 words
The method of claim 18 , wherein selecting is accomplished by a multiplexer.
Claim 22
Dependent Claim
120 words
A delay lock loop circuit for processing a clock signal, comprising: a variable delay circuit configured to receive a frequency divided version of the clock signal; a phase detector for receiving as inputs (i) the output of the variable delay circuit and (ii) the frequency divided version of the clock signal, and for producing a first signal indicative of the phase difference between the two phase detector inputs; and a feedback loop for receiving the first signal and for producing a control signal, wherein the feedback loop comprises an integrator coupled to the first signal for producing the control signal; wherein the control signal is received by the variable delay circuit to adjust the delay of the variable delay circuit.
Claim 23
Dependent Claim
120 words
A delay lock loop circuit for processing a clock signal, comprising: a variable delay circuit configured to receive a frequency divided version of the clock signal; a phase detector for receiving as inputs (i) the output of the variable delay circuit and (ii) the frequency divided version of the clock signal, and for producing a first signal indicative of the phase difference between the two phase detector inputs; and a feedback loop for receiving the first signal and for producing a control signal, wherein the feedback loop comprises an integrator coupled to the first signal for producing the control signal; wherein the control signal is received by the variable delay circuit to adjust the delay of the variable delay circuit.
Claim 24
Dependent Claim
15 words
The circuit of claim 20 , wherein the variable delay circuit includes a propagation delay.
Claim 25
Dependent Claim
28 words
The circuit of claim 20 , wherein the output of the variable delay circuit is synchronized with reading or writing of data to and from a memory array.
Claim 26
Dependent Claim
34 words
The circuit of claim 22 , further comprising a vernier circuit coupled between the variable delay circuit and the phase detector for producing various delayed representations of the output of the variable delay circuit.
Claim 27
Dependent Claim
23 words
The circuit of claim 23 , further comprising a multiplexer for selecting one of the delayed representations to synchronize the reading and writing.
Claim 28
Dependent Claim
22 words
The circuit of claim 20 , further comprising a lock sequencer circuit, wherein the lock sequencer circuit can interrupt the control signal.
Claim 29
Dependent Claim
16 words
The circuit of claim 20 , wherein the control signal is resettable to a minimum value.
Claim 30
Dependent Claim
151 words
A memory device accessible by a first clock signal, comprising: a memory array accessible by a second clock signal; and a delay lock loop for synchronizing the second clock signal with the first clock signal, comprising: a variable delay circuit for producing the second clock signal, wherein the variable delay circuit is configured to receive a frequency divided version of the first clock signal; a phase detector for receiving as inputs (i) either the second clock signal, and (ii) the frequency divided version of the first clock signal, and for producing a first signal indicative of the phase difference between the two phase detector inputs; and a feedback loop for receiving the first signal and for producing a control signal; wherein the control signal is received by the variable delay circuit to adjust the delay of the variable delay circuit, and wherein the control signal is resettable to a minimum value.
Claim 31
Dependent Claim
151 words
A memory device accessible by a first clock signal, comprising: a memory array accessible by a second clock signal; and a delay lock loop for synchronizing the second clock signal with the first clock signal, comprising: a variable delay circuit for producing the second clock signal, wherein the variable delay circuit is configured to receive a frequency divided version of the first clock signal; a phase detector for receiving as inputs (i) either the second clock signal, and (ii) the frequency divided version of the first clock signal, and for producing a first signal indicative of the phase difference between the two phase detector inputs; and a feedback loop for receiving the first signal and for producing a control signal; wherein the control signal is received by the variable delay circuit to adjust the delay of the variable delay circuit, and wherein the control signal is resettable to a minimum value.
Claim 32
Independent Claim
165 words
A system, comprising: a microprocessor for producing a first clock signal; a memory device for receiving the first clock signal, the memory device comprising a memory array accessible by a second clock signal; and a delay lock loop for synchronizing the second clock signal with the first clock signal, comprising: a variable delay circuit for producing the second clock signal, wherein the variable delay circuit is configured to receive a frequency divided version of the first clock signal; a phase detector for receiving as inputs (i) either the second clock signal, and (ii) the frequency divided version of the first clock signal, and for producing a first signal indicative of the phase difference between the two phase detector inputs; and a feedback loop for receiving the first signal and for producing a control signal; wherein the control signal is received by the variable delay circuit to adjust the delay of the variable delay circuit, and wherein the control signal is resettable to a minimum value.
Claim 33
Independent Claim
165 words
A system, comprising: a microprocessor for producing a first clock signal; a memory device for receiving the first clock signal, the memory device comprising a memory array accessible by a second clock signal; and a delay lock loop for synchronizing the second clock signal with the first clock signal, comprising: a variable delay circuit for producing the second clock signal, wherein the variable delay circuit is configured to receive a frequency divided version of the first clock signal; a phase detector for receiving as inputs (i) either the second clock signal, and (ii) the frequency divided version of the first clock signal, and for producing a first signal indicative of the phase difference between the two phase detector inputs; and a feedback loop for receiving the first signal and for producing a control signal; wherein the control signal is received by the variable delay circuit to adjust the delay of the variable delay circuit, and wherein the control signal is resettable to a minimum value.
Claim 34
Independent Claim
82 words
A method of synchronizing a clock signal using a delay lock loop, comprising: frequency dividing the clock signal to provide a divided signal; coupling the divided signal to an input of a variable delay circuit, the variable delay circuit outputting a delayed signal; comparing the divided signal to a phase of the delayed signal to generate a control signal, wherein the control signal comprises use of an integrator; and applying the control signal to the variable delay circuit to control its delay.
Claim 35
Independent Claim
82 words
A method of synchronizing a clock signal using a delay lock loop, comprising: frequency dividing the clock signal to provide a divided signal; coupling the divided signal to an input of a variable delay circuit, the variable delay circuit outputting a delayed signal; comparing the divided signal to a phase of the delayed signal to generate a control signal, wherein the control signal comprises use of an integrator; and applying the control signal to the variable delay circuit to control its delay.
Claim 36
Dependent Claim
17 words
The method of claim 29 , further comprising initially fixing said control signal to a reset value.
Claim 37
Dependent Claim
19 words
The method of claim 30 , wherein the reset value sets the variable delay circuit to a minimum setting.
Claim 38
Dependent Claim
15 words
The method of claim 29 , wherein the variable delay circuit includes a propagation delay.
Claim 39
Dependent Claim
16 words
The method of claim 29 , wherein the control signal comprises use of a charge pump.
Claim 40
Dependent Claim
36 words
The method of claim 29 , wherein comparing the divided signal to a phase of the delayed signal to generate a control signal involves assessing the phase difference between the divided signal and the delayed signal.
Claim 41
Dependent Claim
30 words
The method of claim 29 , wherein the method produces the delayed signal such that it is synchronized with reading or writing of data to and from a memory array.
Claim 42
Dependent Claim
25 words
The method of claim 35 , further comprising coupling the delayed signal to a vernier circuit to produce various delayed representations of the delayed signal.
Claim 43
Dependent Claim
20 words
The method of claim 36 , further comprising selecting one of the delayed representations to synchronize the reading and writing.
Claim 44
Dependent Claim
13 words
The method of claim 37 , wherein selecting is accomplished by a multiplexer.
Claim 45
Independent Claim
89 words
A method of synchronizing a clock signal using a delay lock loop, comprising: frequency dividing the clock signal to provide a divided signal; coupling divided signal to an input of a variable delay circuit, the variable delay circuit outputting a delayed signal; coupling the delayed signal to a vernier circuit to produce various delayed representations of the delayed signal; comparing the divided signal to a phase of the delayed signal to generate a control signal; and applying the control signal to the variable delay circuit to control its delay.
Claim 46
Independent Claim
89 words
A method of synchronizing a clock signal using a delay lock loop, comprising: frequency dividing the clock signal to provide a divided signal; coupling divided signal to an input of a variable delay circuit, the variable delay circuit outputting a delayed signal; coupling the delayed signal to a vernier circuit to produce various delayed representations of the delayed signal; comparing the divided signal to a phase of the delayed signal to generate a control signal; and applying the control signal to the variable delay circuit to control its delay.
Claim 47
Dependent Claim
17 words
The method of claim 39 , further comprising initially fixing said control signal to a reset value.
Claim 48
Dependent Claim
19 words
The method of claim 40 , wherein the reset value sets the variable delay circuit to a minimum setting.
Claim 49
Dependent Claim
15 words
The method of claim 39 , wherein the variable delay circuit includes a propagation delay.
Claim 50
Dependent Claim
15 words
The method of claim 39 , wherein the control signal comprises use of an integrator.
Claim 51
Dependent Claim
16 words
The method of claim 39 , wherein the control signal comprises use of a charge pump.
Claim 52
Dependent Claim
36 words
The method of claim 39 , wherein comparing the divided signal to a phase of the delayed signal to generate a control signal involves assessing the phase difference between the divided signal and the delayed signal.
Claim 53
Dependent Claim
30 words
The method of claim 39 , wherein the method produces the delayed signal such that it is synchronized with reading or writing of data to and from a memory array.
Claim 54
Dependent Claim
20 words
The method of claim 46 , further comprising selecting one of the delayed representations to synchronize the reading and writing.
Claim 55
Dependent Claim
13 words
The method of claim 47 , wherein selecting is accomplished by a multiplexer.
Claim 56
Dependent Claim
120 words
A delay lock loop circuit for processing a clock signal, comprising: a variable delay circuit configured to receive a frequency divided version of the clock signal; a vernier circuit coupled for producing various delayed representations of the output of the variable delay circuit; a phase detector for receiving as inputs (i) the output of the variable delay circuit and (ii) the frequency divided version of the clock signal, and for producing a first signal indicative of the phase difference between the two phase detector inputs; and a feedback loop for receiving the first signal and for producing a control signal, wherein the control signal is received by the variable delay circuit to adjust the delay of the variable delay circuit.
Claim 57
Dependent Claim
120 words
A delay lock loop circuit for processing a clock signal, comprising: a variable delay circuit configured to receive a frequency divided version of the clock signal; a vernier circuit coupled for producing various delayed representations of the output of the variable delay circuit; a phase detector for receiving as inputs (i) the output of the variable delay circuit and (ii) the frequency divided version of the clock signal, and for producing a first signal indicative of the phase difference between the two phase detector inputs; and a feedback loop for receiving the first signal and for producing a control signal, wherein the control signal is received by the variable delay circuit to adjust the delay of the variable delay circuit.
Claim 58
Dependent Claim
15 words
The circuit of claim 49 , wherein the variable delay circuit includes a propagation delay.
Claim 59
Dependent Claim
23 words
The circuit of claim 49 , wherein the feedback loop comprises an integrator coupled to the first signal for producing the control signal.
Claim 60
Dependent Claim
28 words
The circuit of claim 49 , wherein the output of the variable delay circuit is synchronized with reading or writing of data to and from a memory array.
Claim 61
Dependent Claim
23 words
The circuit of claim 49 , further comprising a multiplexer for selecting one of the delayed representations to synchronize the reading and writing.
Claim 62
Dependent Claim
22 words
The circuit of claim 49 , further comprising a lock sequencer circuit, wherein the lock sequencer circuit can interrupt the control signal.
Claim 63
Dependent Claim
16 words
The circuit of claim 49 , wherein the control signal is resettable to a minimum value.
Claim 64
Dependent Claim
125 words
A delay lock loop circuit for processing a clock signal, comprising: a variable delay circuit configured to receive a frequency divided version of the clock signal; a phase detector for receiving as inputs (i) the output of the variable delay circuit and (ii) the frequency divided version of the clock signal, and for producing a first signal indicative of the phase difference between the two phase detector inputs; a feedback loop for receiving the first signal and for producing a control signal; and a lock sequencer circuit, wherein the lock sequencer circuit can interrupt the control signal, wherein the control signal is received by the variable delay circuit to adjust the delay of the variable delay circuit when not interrupted by the lock sequencer circuit.
Claim 65
Dependent Claim
125 words
A delay lock loop circuit for processing a clock signal, comprising: a variable delay circuit configured to receive a frequency divided version of the clock signal; a phase detector for receiving as inputs (i) the output of the variable delay circuit and (ii) the frequency divided version of the clock signal, and for producing a first signal indicative of the phase difference between the two phase detector inputs; a feedback loop for receiving the first signal and for producing a control signal; and a lock sequencer circuit, wherein the lock sequencer circuit can interrupt the control signal, wherein the control signal is received by the variable delay circuit to adjust the delay of the variable delay circuit when not interrupted by the lock sequencer circuit.
Claim 66
Dependent Claim
15 words
The circuit of claim 56 , wherein the variable delay circuit includes a propagation delay.
Claim 67
Dependent Claim
23 words
The circuit of claim 56 , wherein the feedback loop comprises an integrator coupled to the first signal for producing the control signal.
Claim 68
Dependent Claim
28 words
The circuit of claim 56 , wherein the output of the variable delay circuit is synchronized with reading or writing of data to and from a memory array.
Claim 69
Dependent Claim
34 words
The circuit of claim 59 , further comprising a vernier circuit coupled between the variable delay circuit and the phase detector for producing various delayed representations of the output of the variable delay circuit.
Claim 70
Dependent Claim
23 words
The circuit of claim 60 , further comprising a multiplexer for selecting one of the delayed representations to synchronize the reading and writing.
Claim 71
Dependent Claim
16 words
The circuit of claim 56 , wherein the control signal is resettable to a minimum value.
Claim 72
Dependent Claim
114 words
A delay lock loop circuit for processing a clock signal, comprising: a variable delay circuit configured to receive a frequency divided version of the clock signal; a phase detector for receiving as inputs (i) the output of the variable delay circuit and (ii) the frequency divided version of the clock signal, and for producing a first signal indicative of the phase difference between the two phase detector inputs; and a feedback loop for receiving the first signal and for producing a control signal, wherein the control signal is received by the variable delay circuit to adjust the delay of the variable delay circuit, and wherein the control signal is resettable to a minimum value.
Claim 73
Dependent Claim
114 words
A delay lock loop circuit for processing a clock signal, comprising: a variable delay circuit configured to receive a frequency divided version of the clock signal; a phase detector for receiving as inputs (i) the output of the variable delay circuit and (ii) the frequency divided version of the clock signal, and for producing a first signal indicative of the phase difference between the two phase detector inputs; and a feedback loop for receiving the first signal and for producing a control signal, wherein the control signal is received by the variable delay circuit to adjust the delay of the variable delay circuit, and wherein the control signal is resettable to a minimum value.
Claim 74
Dependent Claim
15 words
The circuit of claim 63 , wherein the variable delay circuit includes a propagation delay.
Claim 75
Dependent Claim
23 words
The circuit of claim 63 , wherein the feedback loop comprises an integrator coupled to the first signal for producing the control signal.
Claim 76
Dependent Claim
28 words
The circuit of claim 63 , wherein the output of the variable delay circuit is synchronized with reading or writing of data to and from a memory array.
Claim 77
Dependent Claim
34 words
The circuit of claim 66 , further comprising a vernier circuit coupled between the variable delay circuit and the phase detector for producing various delayed representations of the output of the variable delay circuit.
Claim 78
Dependent Claim
23 words
The circuit of claim 67 , further comprising a multiplexer for selecting one of the delayed representations to synchronize the reading and writing.
Claim 79
Dependent Claim
22 words
The circuit of claim 63 , further comprising a lock sequencer circuit, wherein the lock sequencer circuit can interrupt the control signal.
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2008-01-11 | 2008-07-12 | 2009-01-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2012-01-11 | 2012-07-12 | 2013-01-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2016-01-11 | 2016-07-12 | 2017-01-11 | $7700.00 | Window Closed / Lapsed |