US6316976B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for improving the performance of digital delay locked loop circuits
Assignee: Micron Technology Inc
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Filing: 2000-04-28
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Granted: 2001-11-13
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Expires: 2020-04-28
Abstract
Abstract A method and apparatus for improving the performance and accuracy of a digital delay locked loop (DDLL) by using a unique correction latch and novel reset mechanism circuit for eliminating DDLL minimum and maximum delay states of inoperability. The accuracy of a DDLL is further improved by the use of a three-NAND gate logic delay element design. A DDLL according to the present invention provides symmetrical rising and falling edges of the signal at the output of each delay line element. A DDLL according to the present invention further ensures insensitivity to random values upon initialization. In addition, a DDLL according to the present invention has increased accuracy due to ensuring a comparison between the actual, not divided-down, input signal and an output signal during a phase detect operation.
Inventors
- 👤 James E. Miller, Jr.
- 👤 Aaron Schoenfeld
- 👤 Manny Ma
- 👤 R. Jacob Baker
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 16:10
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/081; H03L7/0812; H03L7/0814; H03L7/10; H03K; H03K5/00; H03K5/13; H03K5/133; H03L7/0816
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
85 words
An apparatus for synchronizing clock signals of a plurality of integrated circuits, said apparatus for use with a phase detect circuit, shift register and a delay line having a delay state output, said apparatus comprising: a correction latch for receiving a control signal from the phase detect circuit and being coupled to the shift register and the delay state output, said correction latch generating an override shift command to the shift register when a state of minimum delay is provided by the delay state output.
Claim 2
Independent Claim
85 words
An apparatus for synchronizing clock signals of a plurality of integrated circuits, said apparatus for use with a phase detect circuit, shift register and a delay line having a delay state output, said apparatus comprising: a correction latch for receiving a control signal from the phase detect circuit and being coupled to the shift register and the delay state output, said correction latch generating an override shift command to the shift register when a state of minimum delay is provided by the delay state output.
Claim 3
Dependent Claim
43 words
The apparatus of claim 1 , wherein said override shift command causes the shift register to output a command to increase a delay in the delay line until the phase detect circuit generates the control signal with a value to increase the delay.
Claim 4
Dependent Claim
43 words
The apparatus of claim 1 further comprising a reset mechanism coupled to a maximum delay stage of the shift register for resetting the shift register when contents of the maximum delay stage correspond to a state of maximum delay in the delay line.
Claim 5
Dependent Claim
53 words
The apparatus of claim 1 further comprising a divide by n frequency divider having an input for receiving the control signal and n outputs representing the control signal coupled to said correction latch, said n outputs controlling said correction latch to allow delay line correction on every nth input to said frequency divider.
Claim 6
Dependent Claim
10 words
The apparatus of claim 4 , wherein n equals 2.
Claim 7
Independent Claim
129 words
An apparatus for synchronizing clock signals of a plurality of integrated circuits, said apparatus for use with a shift register, delay line and a phase detect circuit generating a control signal, said apparatus comprising: a reset mechanism coupled to a maximum delay stage of the shift register for resetting the shift register to a predetermined state when contents of the maximum delay stage correspond to a state of maximum delay in the delay line; a latch circuit coupled to the shift register; and a divide by n frequency divider having an input for receiving the control signal and n outputs representing the control signal coupled to said latch circuit, said n outputs controlling said latch circuit to allow delay line correction on every nth input to said frequency divider.
Claim 8
Independent Claim
129 words
An apparatus for synchronizing clock signals of a plurality of integrated circuits, said apparatus for use with a shift register, delay line and a phase detect circuit generating a control signal, said apparatus comprising: a reset mechanism coupled to a maximum delay stage of the shift register for resetting the shift register to a predetermined state when contents of the maximum delay stage correspond to a state of maximum delay in the delay line; a latch circuit coupled to the shift register; and a divide by n frequency divider having an input for receiving the control signal and n outputs representing the control signal coupled to said latch circuit, said n outputs controlling said latch circuit to allow delay line correction on every nth input to said frequency divider.
Claim 9
Dependent Claim
10 words
The apparatus of claim 6 , wherein n equals 2.
Claim 10
Dependent Claim
89 words
A computer system comprising: an apparatus for synchronizing clock signals of a plurality of integrated circuits, said apparatus for use with a phase detect circuit, shift register and a delay line having a delay state output, said apparatus comprising: a correction latch for receiving a control signal from the phase detect circuit and being coupled to the shift register and the delay state output, said correction latch generating an override shift command to the shift register when a state of minimum delay is provided by the delay state output.
Claim 11
Dependent Claim
89 words
A computer system comprising: an apparatus for synchronizing clock signals of a plurality of integrated circuits, said apparatus for use with a phase detect circuit, shift register and a delay line having a delay state output, said apparatus comprising: a correction latch for receiving a control signal from the phase detect circuit and being coupled to the shift register and the delay state output, said correction latch generating an override shift command to the shift register when a state of minimum delay is provided by the delay state output.
Claim 12
Dependent Claim
43 words
The system of claim 8 , wherein said override shift command causes the shift register to output a command to increase a delay in the delay line until the phase detect circuit generates the control signal with a value to increase the delay.
Claim 13
Dependent Claim
47 words
The system of claim 8 , wherein said apparatus further comprises a reset mechanism coupled to a maximum delay stage of the shift register for resetting the shift register when contents of the maximum delay stage correspond to a state of maximum delay in the delay line.
Claim 14
Dependent Claim
57 words
The system of claim 8 , wherein said apparatus further comprises a divide by n frequency divider having an input for receiving the control signal and n outputs representing the control signal coupled to said correction latch, said n outputs controlling said correction latch to allow delay line correction on every nth input to said frequency divider.
Claim 15
Dependent Claim
10 words
The system of claim 11 , wherein n equals 2.
Claim 16
Dependent Claim
135 words
A computer system comprising: an apparatus for synchronizing clock signals of a plurality of integrated circuits, said apparatus for use with a shift register, delay line and a phase detect circuit generating a control signal, said apparatus comprising: a reset mechanism coupled to a maximum delay stage of the shift register for resetting the shift register to a predetermined state when contents of the maximum delay stage correspond to a state of maximum delay in the delay line; a latch circuit to be coupled to the shift register; and a divide by n frequency divider having an input for receiving the control signal and n outputs representing the control signal coupled to said latch circuit, said n outputs controlling said latch circuit to allow delay line correction on every nth input to said frequency divider.
Claim 17
Dependent Claim
135 words
A computer system comprising: an apparatus for synchronizing clock signals of a plurality of integrated circuits, said apparatus for use with a shift register, delay line and a phase detect circuit generating a control signal, said apparatus comprising: a reset mechanism coupled to a maximum delay stage of the shift register for resetting the shift register to a predetermined state when contents of the maximum delay stage correspond to a state of maximum delay in the delay line; a latch circuit to be coupled to the shift register; and a divide by n frequency divider having an input for receiving the control signal and n outputs representing the control signal coupled to said latch circuit, said n outputs controlling said latch circuit to allow delay line correction on every nth input to said frequency divider.
Claim 18
Dependent Claim
10 words
The system of claim 13 , wherein n equals 2.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-11-12 | 2005-05-14 | 2005-11-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-11-12 | 2009-05-14 | 2009-11-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-11-12 | 2013-05-14 | 2013-11-13 | $7700.00 | Window Closed / Lapsed |