Capture clock generator using master and slave delay locked loops

Claim 2

A clock generator comprising: a receiving circuit to receive an external clock signal to produce an internal clock signal, the receiving circuit including a first delay and a second delay; a data receiver to receive an external data signal to produce an internal data signal, wherein the data receiver includes a delay equal to the second delay of the receiving circuit; a first delay locked loop (DLL) to receive the internal clock signal to produce an output clock signal, wherein the output clock signal is 90 degrees out of phase with the internal clock signal; and a second DLL selectively connected to the first DLL to receive the output clock signal to generate a capture clock signal, wherein the capture clock signal is 90 degrees out of phase with the internal data signal.

Claim 3

The clock generator of claim 1 , wherein the external clock signal is edge aligned with the external data signal.

Claim 4

A clock generator comprising: a receiving circuit to receive an external clock signal to produce an internal clock signal; a data receiver to receive an external data signal to produce an internal data signal; a first delay locked loop (DLL) to receive the internal clock signal to produce an output clock signal, wherein the output clock signal is 90 degrees out of phase with the internal clock signal; and a second DLL selectively connected to the first DLL to receive the output clock signal to generate a capture clock signal, wherein the capture clock signal is 90 degrees out of phase with the internal data signal, wherein the receiving circuit includes a clock receiver and a data receiver model, wherein a delay of the data receiver model is the same as a delay of the data receiver.

Claim 5

A clock generator comprising: a receiving circuit to receive an external clock signal to produce an internal clock signal; a data receiver to receive an external data signal to produce an internal data signal; a first delay locked loop (DLL) to receive the internal clock signal to produce an output clock signal, wherein the output clock signal is 90 degrees out of phase with the internal clock signal; and a second DLL selectively connected to the first DLL to receive the output clock signal to generate a capture clock signal, wherein the capture clock signal is 90 degrees out of phase with the internal data signal, wherein the receiving circuit includes a clock receiver and a data receiver model, wherein a delay of the data receiver model is the same as a delay of the data receiver.

Claim 6

A clock generator comprising: a receiving circuit to receive an external clock signal to produce an internal clock signal: a data receiver to receive an external data signal to produce an internal data signal: a first delay locked loop (DLL) to receive the internal clock signal to produce an output clock signal, wherein the output clock signal is 90 degrees out of phase with the internal clock signal; and a second DLL selectively connected to the first DLL to receive the output clock signal to generate a capture clock signal, wherein the capture clock signal is 90 degrees out of phase with the internal data signal, wherein the first DLL includes: a first delay line to provide a quarter of clock cycle delay to the internal clock signal to generate the output clock signal; a second delay line to provide a quarter of clock cycle delay to the output clock signal to generate a feedback signal; a phase detector to compare an inverse of the internal clock signal and the feedback signal; and a controller to provide control to the first and second delay lines.

Claim 7

A clock generator comprising: a receiving circuit to receive an external clock signal to produce an internal clock signal: a data receiver to receive an external data signal to produce an internal data signal: a first delay locked loop (DLL) to receive the internal clock signal to produce an output clock signal, wherein the output clock signal is 90 degrees out of phase with the internal clock signal; and a second DLL selectively connected to the first DLL to receive the output clock signal to generate a capture clock signal, wherein the capture clock signal is 90 degrees out of phase with the internal data signal, wherein the first DLL includes: a first delay line to provide a quarter of clock cycle delay to the internal clock signal to generate the output clock signal; a second delay line to provide a quarter of clock cycle delay to the output clock signal to generate a feedback signal; a phase detector to compare an inverse of the internal clock signal and the feedback signal; and a controller to provide control to the first and second delay lines.

Claim 8

A clock generator comprising: a receiving circuit to receive an external clock signal to produce an internal clock signal: a data receiver to receive an external data signal to produce an internal data signal: a first delay locked loop (DLL) to receive the internal clock signal to produce an output clock signal, wherein the output clock signal is 90 degrees out of phase with the internal clock signal; and a second DLL selectively connected to the first DLL to receive the output clock signal to generate a capture clock signal, wherein the capture clock signal is 90 degrees out of phase with the internal data signal, wherein the second DLL includes: a forward path comprising: a clock receiver; a delay line to apply an amount of delay to the output clock signal to generate a delayed signal; and a clock tree to receive the delayed signal to generate the capture signal; and a feedback path to provide a feedback signal, the feedback path including a model circuit, wherein a delay of the model circuit includes a delay of the clock receiver.

Claim 9

A clock generator comprising: a receiving circuit to receive an external clock signal to produce an internal clock signal: a data receiver to receive an external data signal to produce an internal data signal: a first delay locked loop (DLL) to receive the internal clock signal to produce an output clock signal, wherein the output clock signal is 90 degrees out of phase with the internal clock signal; and a second DLL selectively connected to the first DLL to receive the output clock signal to generate a capture clock signal, wherein the capture clock signal is 90 degrees out of phase with the internal data signal, wherein the second DLL includes: a forward path comprising: a clock receiver; a delay line to apply an amount of delay to the output clock signal to generate a delayed signal; and a clock tree to receive the delayed signal to generate the capture signal; and a feedback path to provide a feedback signal, the feedback path including a model circuit, wherein a delay of the model circuit includes a delay of the clock receiver.

Claim 10

The clock generator of claim 5 , wherein the feedback signal of the second DLL and the output clock signal of the first DLL are synchronized.

Claim 11

A clock circuit comprising: a receiving circuit to receive an external clock signal to produce an internal clock signal, the receiving circuit including a first delay and a second delay; a data receiver to receive an external data signal to produce an internal data signal, wherein the data receiver includes a delay equal to the second delay of the receiving circuit; a first delay locked loop (DLL) to receive the internal clock signal to produce a slave output clock signal, wherein the slave output clock signal is one-fourth clock cycle delayed from the internal clock signal; and a master DLL connected to the first DLL, the master DLL comprising: a forward path to receive the slave output clock signal to produce a capture clock signal; and a feedback path to receive the capture clock signal to produce a feedback signal, wherein the capture clock signal is center aligned with the internal data signal when the feedback and slave output signals are synchronized.

Claim 12

A clock circuit comprising: a receiving circuit to receive an external clock signal to produce an internal clock signal, the receiving circuit including a first delay and a second delay; a data receiver to receive an external data signal to produce an internal data signal, wherein the data receiver includes a delay equal to the second delay of the receiving circuit; a first delay locked loop (DLL) to receive the internal clock signal to produce a slave output clock signal, wherein the slave output clock signal is one-fourth clock cycle delayed from the internal clock signal; and a master DLL connected to the first DLL, the master DLL comprising: a forward path to receive the slave output clock signal to produce a capture clock signal; and a feedback path to receive the capture clock signal to produce a feedback signal, wherein the capture clock signal is center aligned with the internal data signal when the feedback and slave output signals are synchronized.

Claim 13

The clock circuit of claim 7 , wherein the external clock signal is edge aligned with the external data signal.

Claim 14

A clock circuit comprising: a receiving circuit to receive an external clock signal to produce an internal clock signal; a data receiver to receive an external data signal to produce an internal data signal; a first delay locked loop (DLL) to receive the internal clock signal to produce a slave output clock signal, wherein the slave output clock signal is one-fourth clock cycle delayed from the internal clock signal; and a master DLL connected to the first DLL, the master DLL comprising: a forward path to receive the slave output clock signal to produce a capture clock signal; and a feedback path to receive the capture clock signal to produce a feedback signal, wherein the capture clock signal is center aligned with the internal data signal when the feedback and slave output signals are synchronized, wherein the receiving circuit includes a clock receiver and a data receiver model, wherein a delay of the data receiver model is the same as a delay of the data receiver.

Claim 15

A clock circuit comprising: a receiving circuit to receive an external clock signal to produce an internal clock signal; a data receiver to receive an external data signal to produce an internal data signal; a first delay locked loop (DLL) to receive the internal clock signal to produce a slave output clock signal, wherein the slave output clock signal is one-fourth clock cycle delayed from the internal clock signal; and a master DLL connected to the first DLL, the master DLL comprising: a forward path to receive the slave output clock signal to produce a capture clock signal; and a feedback path to receive the capture clock signal to produce a feedback signal, wherein the capture clock signal is center aligned with the internal data signal when the feedback and slave output signals are synchronized, wherein the receiving circuit includes a clock receiver and a data receiver model, wherein a delay of the data receiver model is the same as a delay of the data receiver.

Claim 16

A clock circuit comprising: a receiving circuit to receive an external clock signal to produce an internal clock signal; a data receiver to receive an external data signal to produce an internal data signal; a first delay locked loop (DLL) to receive the internal clock signal to produce a slave output clock signal, wherein the slave output clock signal is one-fourth clock cycle delayed from the internal clock signal; and a master DLL connected to the first DLL, the master DLL comprising: a forward path to receive the slave output clock signal to produce a capture clock signal; and a feedback path to receive the capture clock signal to produce a feedback signal, wherein the capture clock signal is center aligned with the internal data signal when the feedback and slave output signals are synchronized, wherein the first DLL includes: a first delay line to apply a quarter of clock cycle delay to the internal clock signal produce the slave output clock signal; a second delay line to apply a quarter of clock cycle delay to the slave output clock signal to produce a slave feedback signal; a phase detector to compare an inverse of the internal clock and slave feedback signals to provide shifting signals; and a controller to control the first and second delay lines based on the shifting signals to keep the inverse of the internal clock and slave feedback signals synchronized.

Claim 17

A clock circuit comprising: a receiving circuit to receive an external clock signal to produce an internal clock signal; a data receiver to receive an external data signal to produce an internal data signal; a first delay locked loop (DLL) to receive the internal clock signal to produce a slave output clock signal, wherein the slave output clock signal is one-fourth clock cycle delayed from the internal clock signal; and a master DLL connected to the first DLL, the master DLL comprising: a forward path to receive the slave output clock signal to produce a capture clock signal; and a feedback path to receive the capture clock signal to produce a feedback signal, wherein the capture clock signal is center aligned with the internal data signal when the feedback and slave output signals are synchronized, wherein the first DLL includes: a first delay line to apply a quarter of clock cycle delay to the internal clock signal produce the slave output clock signal; a second delay line to apply a quarter of clock cycle delay to the slave output clock signal to produce a slave feedback signal; a phase detector to compare an inverse of the internal clock and slave feedback signals to provide shifting signals; and a controller to control the first and second delay lines based on the shifting signals to keep the inverse of the internal clock and slave feedback signals synchronized.

Claim 18

A clock circuit comprising: a receiving circuit to receive an external clock signal to produce an internal clock signal; a data receiver to receive an external data signal to produce an internal data signal; a first delay locked loop (DLL) to receive the internal clock signal to produce a slave output clock signal, wherein the slave output clock signal is one-fourth clock cycle delayed from the internal clock signal; and a master DLL connected to the first DLL, the master DLL comprising: a forward path to receive the slave output clock signal to produce a capture clock signal; and a feedback path to receive the capture clock signal to produce a feedback signal, wherein the capture clock signal is center aligned with the internal data signal when the feedback and slave output signals are synchronized, wherein the forward path includes: a delay line to apply a delay to the output clock signal to generate a delayed signal; and a clock tree to receive the delayed signal to generate a plurality of the capture clock signals.

Claim 19

A clock circuit comprising: a receiving circuit to receive an external clock signal to produce an internal clock signal; a data receiver to receive an external data signal to produce an internal data signal; a first delay locked loop (DLL) to receive the internal clock signal to produce a slave output clock signal, wherein the slave output clock signal is one-fourth clock cycle delayed from the internal clock signal; and a master DLL connected to the first DLL, the master DLL comprising: a forward path to receive the slave output clock signal to produce a capture clock signal; and a feedback path to receive the capture clock signal to produce a feedback signal, wherein the capture clock signal is center aligned with the internal data signal when the feedback and slave output signals are synchronized, wherein the forward path includes: a delay line to apply a delay to the output clock signal to generate a delayed signal; and a clock tree to receive the delayed signal to generate a plurality of the capture clock signals.

Claim 20

A clock circuit comprising: a receiving circuit to receive an external clock signal to produce an internal clock signal; a data receiver to receive an external data signal to produce an internal data signal; a first delay locked loop (DLL) to receive the internal clock signal to produce a slave output clock signal, wherein the slave output clock signal is one-fourth clock cycle delayed from the internal clock signal; and a master DLL connected to the first DLL, the master DLL comprising: a forward path to receive the slave output clock signal to produce a capture clock signal; and a feedback path to receive the capture clock signal to produce a feedback signal, wherein the capture clock signal is center aligned with the internal data signal when the feedback and slave output signals are synchronized, wherein the forward path includes a clock receiver, the feedback path includes a model circuit, wherein a delay of the model circuit includes a delay of the clock receiver.

Claim 21

A clock circuit comprising: a receiving circuit to receive an external clock signal to produce an internal clock signal; a data receiver to receive an external data signal to produce an internal data signal; a first delay locked loop (DLL) to receive the internal clock signal to produce a slave output clock signal, wherein the slave output clock signal is one-fourth clock cycle delayed from the internal clock signal; and a master DLL connected to the first DLL, the master DLL comprising: a forward path to receive the slave output clock signal to produce a capture clock signal; and a feedback path to receive the capture clock signal to produce a feedback signal, wherein the capture clock signal is center aligned with the internal data signal when the feedback and slave output signals are synchronized, wherein the forward path includes a clock receiver, the feedback path includes a model circuit, wherein a delay of the model circuit includes a delay of the clock receiver.

Claim 22

A clock circuit comprising: a receiving circuit to receive an external clock signal to produce an internal clock signal, the receiving circuit including a first delay and a second delay; a data receiver to receive an external data signal to produce an internal data signal, wherein the data receiver includes a delay equal to the second delay of the receiving circuit; a first delay locked loop (DLL) comprising: a forward path to provide a slave output clock signal; and a feedback path to provide a feedback signal, wherein the slave output clock signal is 90 degrees out of phase with the internal clock signal when the feedback signal and an inverse of the internal clock signal are synchronized; and a master DLL connected to the first DLL, the master DLL comprising: a forward path to receive the slave output clock signal to produce a capture clock signal; and a feedback path to receive the capture clock signal to produce a feedback signal, wherein the capture clock signal is center aligned with the internal data signal when the feedback and slave output signals are synchronized.

Claim 23

A clock circuit comprising: a receiving circuit to receive an external clock signal to produce an internal clock signal, the receiving circuit including a first delay and a second delay; a data receiver to receive an external data signal to produce an internal data signal, wherein the data receiver includes a delay equal to the second delay of the receiving circuit; a first delay locked loop (DLL) comprising: a forward path to provide a slave output clock signal; and a feedback path to provide a feedback signal, wherein the slave output clock signal is 90 degrees out of phase with the internal clock signal when the feedback signal and an inverse of the internal clock signal are synchronized; and a master DLL connected to the first DLL, the master DLL comprising: a forward path to receive the slave output clock signal to produce a capture clock signal; and a feedback path to receive the capture clock signal to produce a feedback signal, wherein the capture clock signal is center aligned with the internal data signal when the feedback and slave output signals are synchronized.

Claim 24

A clock generator comprising: a receiving circuit to receive an external clock signal to produce an internal clock signal; a data receiver to receive an external data signal to produce an internal data signal; a slave delay locked loop (DLL) to receive the internal clock signal to produce a slave output clock signal, wherein the slave output clock signal is 90 degrees out of phase with the internal clock signal; and a master DLL connected to the slave DLL, the master DLL comprising: a delay line to apply an amount of delay to the slave output clock signal to generate a delayed signal; a clock tree circuit to receive the delayed signal to generate a plurality of capture clock signals; a model circuit to receive one of the capture clock signals to generate a master feedback signal; a phase detector to provide shifting signals based on a phase difference between the slave output clock and the master feedback signals; and a control circuit to control the delay line to adjust the amount of delay applied to the slave output clock signal such that when the slave output clock and master feedback signals are synchronized the capture clock signal is center aligned with the internal data signal.

Claim 25

A clock generator comprising: a receiving circuit to receive an external clock signal to produce an internal clock signal; a data receiver to receive an external data signal to produce an internal data signal; a slave delay locked loop (DLL) to receive the internal clock signal to produce a slave output clock signal, wherein the slave output clock signal is 90 degrees out of phase with the internal clock signal; and a master DLL connected to the slave DLL, the master DLL comprising: a delay line to apply an amount of delay to the slave output clock signal to generate a delayed signal; a clock tree circuit to receive the delayed signal to generate a plurality of capture clock signals; a model circuit to receive one of the capture clock signals to generate a master feedback signal; a phase detector to provide shifting signals based on a phase difference between the slave output clock and the master feedback signals; and a control circuit to control the delay line to adjust the amount of delay applied to the slave output clock signal such that when the slave output clock and master feedback signals are synchronized the capture clock signal is center aligned with the internal data signal.

Claim 26

The clock generator of claim 14 , wherein the external clock signal is edge aligned with the external data signal.

Claim 27

The clock generator of claim 14 , wherein the receiving circuit includes a clock receiver, the model circuit includes a model delay, wherein the model delay includes a delay of the clock receiver.

Claim 28

The clock generator of claim 14 , wherein the receiving circuit includes a clock receiver and a model of the data receiver.

Claim 29

The clock generator of claim 17 , wherein the model circuit includes a model of the clock receiver.

Claim 30

A clock generator comprising: a receiving circuit to receive an external clock signal to produce an internal clock signal, the receiving circuit including a clock receiver and a model of a data receiver; a data receiver to receive an external data signal to produce an internal data signal; a slave delay locked loop (DLL) comprising: a forward path to provide a slave output clock signal; and a feedback path to provide a feedback signal, wherein the slave output clock signal is 90 degrees out of phase with the internal clock signal when the feedback signal and an inverse of the internal clock signal are synchronized; a master DLL connected to the slave DLL, the master DLL comprising: a delay line to apply an amount of delay to the slave output clock signal to generate a delayed signal; a clock tree circuit to receive the delayed signal to generate a plurality of capture clock signals; a model circuit to receive one of the capture clock signals to generate a master feedback signal, wherein a delay of the model circuit includes a delay of the clock receiver; a phase detector to provide shifting signals based on a phase difference between the slave output clock and the master feedback signals; and a control circuit to control the delay line to adjust the amount of delay applied to the slave output clock signal such that when the slave output clock and master feedback signals are synchronized the capture clock signal is center aligned with the internal data signal.

Claim 31

A clock generator comprising: a receiving circuit to receive an external clock signal to produce an internal clock signal, the receiving circuit including a clock receiver and a model of a data receiver; a data receiver to receive an external data signal to produce an internal data signal; a slave delay locked loop (DLL) comprising: a forward path to provide a slave output clock signal; and a feedback path to provide a feedback signal, wherein the slave output clock signal is 90 degrees out of phase with the internal clock signal when the feedback signal and an inverse of the internal clock signal are synchronized; a master DLL connected to the slave DLL, the master DLL comprising: a delay line to apply an amount of delay to the slave output clock signal to generate a delayed signal; a clock tree circuit to receive the delayed signal to generate a plurality of capture clock signals; a model circuit to receive one of the capture clock signals to generate a master feedback signal, wherein a delay of the model circuit includes a delay of the clock receiver; a phase detector to provide shifting signals based on a phase difference between the slave output clock and the master feedback signals; and a control circuit to control the delay line to adjust the amount of delay applied to the slave output clock signal such that when the slave output clock and master feedback signals are synchronized the capture clock signal is center aligned with the internal data signal.

Claim 32

A clock generator comprising: a clock receiver to receive an external clock signal to produce an internal clock signal, the clock receiver including a clock receiver delay; a first delay locked loop (DLL) to receive the internal clock signal to produce an output clock signal, wherein the output clock signal is 90 degrees out of phase with the internal clock signal; a second DLL selectively connected to the first DLL to receive the output clock signal to generate a capture clock signal, the second DLL including a first delay, and a second delay equal to the clock receiver delay; and a data path circuit to receive an internal data signal and the capture clock signal to generated an output data signal, the data path including a delay equal to the first delay of the second DLL, wherein the output data signal is center aligned with the external clock signal.

Claim 33

A clock generator comprising: a clock receiver to receive an external clock signal to produce an internal clock signal, the clock receiver including a clock receiver delay; a first delay locked loop (DLL) to receive the internal clock signal to produce an output clock signal, wherein the output clock signal is 90 degrees out of phase with the internal clock signal; a second DLL selectively connected to the first DLL to receive the output clock signal to generate a capture clock signal, the second DLL including a first delay, and a second delay equal to the clock receiver delay; and a data path circuit to receive an internal data signal and the capture clock signal to generated an output data signal, the data path including a delay equal to the first delay of the second DLL, wherein the output data signal is center aligned with the external clock signal.

Claim 34

A clock generator comprising: a clock receiver to receive an external clock signal to produce an internal clock signal; a first delay locked loop (DLL) to receive the internal clock signal to produce an output clock signal, wherein the output clock signal is 90 degrees out of phase with the internal clock signal; a second DLL selectively connected to the first DLL to receive the output clock signal to generate a capture clock signal; and a data path circuit to receive an internal data signal and the capture clock signal to generated an output data signal, wherein the output data signal is center aligned with the external clock signal, wherein the second DLL includes: a delay line to apply a delay to the output clock signal to generate a delayed signal; and a clock tree to receive the delayed signal to generate a plurality of the capture clock signals.

Claim 35

A clock generator comprising: a clock receiver to receive an external clock signal to produce an internal clock signal; a first delay locked loop (DLL) to receive the internal clock signal to produce an output clock signal, wherein the output clock signal is 90 degrees out of phase with the internal clock signal; a second DLL selectively connected to the first DLL to receive the output clock signal to generate a capture clock signal; and a data path circuit to receive an internal data signal and the capture clock signal to generated an output data signal, wherein the output data signal is center aligned with the external clock signal, wherein the second DLL includes: a delay line to apply a delay to the output clock signal to generate a delayed signal; and a clock tree to receive the delayed signal to generate a plurality of the capture clock signals.

Claim 36

A clock generator comprising: a clock receiver to receive an external clock signal to produce an internal clock signal; a first delay locked loop (DLL) to receive the internal clock signal to produce an output clock signal, wherein the output clock signal is 90 degrees out of phase with the internal clock signal; a second DLL selectively connected to the first DLL to receive the output clock signal to generate a capture clock signal; and a data path circuit to receive an internal data signal and the capture clock signal to generated an output data signal, wherein the output data signal is center aligned with the external clock signal, wherein the second DLL includes a model circuit, wherein a delay of the model circuit includes a delay of the clock receiver and a delay of the data path circuit.

Claim 37

A clock generator comprising: a clock receiver to receive an external clock signal to produce an internal clock signal; a first delay locked loop (DLL) to receive the internal clock signal to produce an output clock signal, wherein the output clock signal is 90 degrees out of phase with the internal clock signal; a second DLL selectively connected to the first DLL to receive the output clock signal to generate a capture clock signal; and a data path circuit to receive an internal data signal and the capture clock signal to generated an output data signal, wherein the output data signal is center aligned with the external clock signal, wherein the second DLL includes a model circuit, wherein a delay of the model circuit includes a delay of the clock receiver and a delay of the data path circuit.

Claim 38

A clock generator comprising: a clock receiver to receive an external clock signal to produce an internal clock signal; a first delay locked loop (DLL) to receive the internal clock signal to produce an output clock signal, wherein the output clock signal is 90 degrees out of phase with the internal clock signal; a second DLL selectively connected to the first DLL to receive the output clock signal to generate a capture clock signal; and a data path circuit to receive an internal data signal and the capture clock signal to generated an output data signal, wherein the output data signal is center aligned with the external clock signal, wherein the second DLL includes a model circuit, and, wherein the model circuit includes a model of the clock receiver and a model of the data path circuit.

Claim 39

A clock generator comprising: a clock receiver to receive an external clock signal to produce an internal clock signal; a first delay locked loop (DLL) to receive the internal clock signal to produce an output clock signal, wherein the output clock signal is 90 degrees out of phase with the internal clock signal; a second DLL selectively connected to the first DLL to receive the output clock signal to generate a capture clock signal; and a data path circuit to receive an internal data signal and the capture clock signal to generated an output data signal, wherein the output data signal is center aligned with the external clock signal, wherein the second DLL includes a model circuit, and, wherein the model circuit includes a model of the clock receiver and a model of the data path circuit.

Claim 40

A clock generator comprising: a clock receiver to receive an external clock signal to produce an internal clock signal; a delay line to apply an amount of delay to the internal clock signal to generate a delayed signal; a clock tree circuit to receive the delayed signal to generate a plurality of capture clock signals; a model circuit to receive one of the capture clock signals to generate a feedback signal, wherein a delay of the model circuit is equal to a delay of the clock receiver and a delay of the data path circuit; a phase detector to provide shifting signals based on a phase difference between the internal clock and the feedback signal; a control circuit to control the delay line to adjust the amount of delay applied to the internal clock signal; and a data path circuit to receive an internal data signal and one of the capture clock signals to generated an output data signal, wherein the output data signal is center aligned with the external clock signal.

Claim 41

A clock generator comprising: a clock receiver to receive an external clock signal to produce an internal clock signal; a delay line to apply an amount of delay to the internal clock signal to generate a delayed signal; a clock tree circuit to receive the delayed signal to generate a plurality of capture clock signals; a model circuit to receive one of the capture clock signals to generate a feedback signal, wherein a delay of the model circuit is equal to a delay of the clock receiver and a delay of the data path circuit; a phase detector to provide shifting signals based on a phase difference between the internal clock and the feedback signal; a control circuit to control the delay line to adjust the amount of delay applied to the internal clock signal; and a data path circuit to receive an internal data signal and one of the capture clock signals to generated an output data signal, wherein the output data signal is center aligned with the external clock signal.

Claim 42

A memory system comprising: a memory device including a plurality of memory cells; and a memory controller connected to the memory device, the memory controller comprising: a receiving circuit to receive an external clock signal to produce an internal clock signal, the receiving circuit including a first delay and a second delay; a data receiver to receive an external data signal from the memory device to produce an internal data signal, wherein the data receiver includes a delay equal to the second delay of the receiving circuit; a first delay locked loop (DLL) to receive the internal clock signal to produce an output clock signal, wherein the output clock signal is 90 degrees out of phase with the internal clock signal; and a second DLL selectively connected to the first DLL to receive the output clock signal to generate a capture clock signal, wherein the capture clock signal is 90 degrees out of phase with the internal data signal.

Claim 43

A memory system comprising: a memory device including a plurality of memory cells; and a memory controller connected to the memory device, the memory controller comprising: a receiving circuit to receive an external clock signal to produce an internal clock signal, the receiving circuit including a first delay and a second delay; a data receiver to receive an external data signal from the memory device to produce an internal data signal, wherein the data receiver includes a delay equal to the second delay of the receiving circuit; a first delay locked loop (DLL) to receive the internal clock signal to produce an output clock signal, wherein the output clock signal is 90 degrees out of phase with the internal clock signal; and a second DLL selectively connected to the first DLL to receive the output clock signal to generate a capture clock signal, wherein the capture clock signal is 90 degrees out of phase with the internal data signal.

Claim 44

The memory system of claim 25 , wherein the external data signal includes a data signal stored in one of the memory cells.

Claim 45

The memory system of claim 25 , wherein the external data signal includes a data signal read from one of the memory cells during a read operation.

Claim 46

A memory system comprising: a memory device including a plurality of memory cells; and a memory controller connected to the memory device, the memory controller comprising: a clock receiver to receive an external clock signal to produce an internal clock signal, the clock receiver including a clock receiver delay; a first delay locked loop (DLL) to receive the internal clock signal to produce an output clock signal, wherein the output clock signal is 90 degrees out of phase with the internal clock signal; a second DLL selectively connected to the first DLL to receive the output clock signal to generate a capture clock signal, the second DLL including a first delay equal to the clock receiver delay, and a second delay; and a data path circuit to receive an internal data signal and the capture clock signal to generate an output data signal, the data path including a delay equal to the second delay of the second DLL, wherein the output data signal is center aligned with the external clock signal.

Claim 47

A memory system comprising: a memory device including a plurality of memory cells; and a memory controller connected to the memory device, the memory controller comprising: a clock receiver to receive an external clock signal to produce an internal clock signal, the clock receiver including a clock receiver delay; a first delay locked loop (DLL) to receive the internal clock signal to produce an output clock signal, wherein the output clock signal is 90 degrees out of phase with the internal clock signal; a second DLL selectively connected to the first DLL to receive the output clock signal to generate a capture clock signal, the second DLL including a first delay equal to the clock receiver delay, and a second delay; and a data path circuit to receive an internal data signal and the capture clock signal to generate an output data signal, the data path including a delay equal to the second delay of the second DLL, wherein the output data signal is center aligned with the external clock signal.

Claim 48

The memory system of claim 28 , wherein the output data signal includes an address signal provided to the memory device during a memory write operation.

Claim 49

The memory system of claim 28 , wherein the output data signal includes a control signal provided to the memory device during a memory write operation.

Claim 56

The method of claim 33 , wherein generating a capture clock signal include passing a delay signal generated from the internal clock signal to a clock tree circuit.

Claim 57

The method of claim 33 , wherein receiving an external clock signal includes passing the external clock signal through a clock receiver.

Claim 58

The method of claim 35 , wherein receiving an external data signal includes passing the external data signal through a data receiver.

Claim 67

The method of claim 40 further includes generating a feedback signal by delaying the capture clock signal.

Claim 68

The method of claim 41 , wherein delaying the capture clock signal includes passing the capture clock signal through a modeled delay.