US6014048A
Expired / Lapsed
US
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Clock generator with multiple feedback paths including a delay locked loop path
Assignee: GlobalFoundries Inc
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Filing: 1998-05-27
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Granted: 2000-01-11
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Expires: 2018-05-27
Abstract
Abstract The present invention encompasses the use of multiple feedback paths in a clock source for an integrated circuit device to maintain phase lock to an external clock. It is further contemplated by the present invention that feedback paths are provided from the internal clock distribution path and from a matching path that approximates the delay of the clock distribution path. The matching path may comprise a delay locked loop. Feedback from the clock distribution path is used in normal operation and feedback from the matching path is used when the internal clock distribution path is disabled. The clock source of the present invention also may implement power management functions.
Inventors
- 👤 Ronald F. Talaga, Jr.
- 👤 Russell Hershbarger
- 👤 James M. Buchanan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 06:55
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; G06F1/10; H; H03; H03L; H03L7/00; H03L7/06; H03L7/07; H03L7/08; H03L7/081; H03L7/16; H03L7/18
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
165 words
An integrated circuit device, comprising a clock generator configured to receive an external clock and a feedback clock and to provide a clock signal, said clock generator configured to maintain approximate phase consistency between said external clock and said feedback clock; a clock distribution path configured to receive said clock signal and to distribute said clock signal to circuits included in the integrated circuit device as an internal clock; a matching path configured to receive said clock signal from said clock generator, to receive said internal clock from said clock distribution path, and to provide a matching clock, wherein said matching path comprises a delay locked loop circuit configured to approximate performance characteristics of said clock distribution path; and a feedback path configured to provide said feedback clock, wherein said feedback path is configured to select said feedback clock as said internal clock from said clock distribution path in a first mode and as said matching clock from said matching path in a second mode.
Claim 2
Dependent Claim
165 words
An integrated circuit device, comprising a clock generator configured to receive an external clock and a feedback clock and to provide a clock signal, said clock generator configured to maintain approximate phase consistency between said external clock and said feedback clock; a clock distribution path configured to receive said clock signal and to distribute said clock signal to circuits included in the integrated circuit device as an internal clock; a matching path configured to receive said clock signal from said clock generator, to receive said internal clock from said clock distribution path, and to provide a matching clock, wherein said matching path comprises a delay locked loop circuit configured to approximate performance characteristics of said clock distribution path; and a feedback path configured to provide said feedback clock, wherein said feedback path is configured to select said feedback clock as said internal clock from said clock distribution path in a first mode and as said matching clock from said matching path in a second mode.
Claim 3
Dependent Claim
20 words
The integrated circuit device as recited in claim 1, wherein said clock distribution path is disabled in said second mode.
Claim 4
Dependent Claim
16 words
The integrated circuit device as recited in claim 1, wherein said feedback path comprises a multiplexer.
Claim 5
Dependent Claim
55 words
The integrated circuit device as recited in claim 1, further comprising a disable signal, wherein said feedback path operates in said first mode when said disable signal is unasserted and operates in said second mode when said disable signal is asserted, and wherein said clock distribution path is disabled when said disable signal is asserted.
Claim 6
Dependent Claim
33 words
The integrated circuit device as recited in claim 1, wherein said delay locked loop circuit comprises a programmable delay element and a comparator configured to match a delay of said clock distribution path.
Claim 7
Dependent Claim
71 words
The integrated circuit device as recited in claim 5, wherein said programmable delay element comprises a plurality of delay elements through which said clock signal passes to form said matching clock, and wherein said comparator is configured to compare said internal clock from said clock distribution path to said matching clock and responsively adjust the number of delay elements through which said clock signal passes in said delay locked loop circuit.
Claim 8
Dependent Claim
33 words
The integrated circuit device as recited in claim 6, wherein the number of delay elements through which said clock signal passes in said delay locked loop circuit is fixed in said second mode.
Claim 9
Dependent Claim
32 words
The integrated circuit device as recited in claim 1, wherein said clock signal is of a higher frequency than said external clock by a multiple of the frequency of said external clock.
Claim 10
Dependent Claim
18 words
The integrated circuit device as recited in claim 1, wherein said clock distribution path comprises a grid structure.
Claim 11
Dependent Claim
63 words
The integrated circuit device as recited in claim 1, wherein said distribution path comprises metal layers in the integrated circuit device, wherein a plurality connection points are provided in said distribution path from which said feedback path may select said feedback clock in said first mode, wherein one of said plurality of connection points is selected according to a metal layer fabrication mask.
Claim 12
Dependent Claim
28 words
The integrated circuit device as recited in claim 1, wherein said clock distribution path comprises a plurality of distribution structures configured to be separately disabled for power management.
Claim 13
Dependent Claim
53 words
The integrated circuit device as recited in claim 11, wherein said feedback path selects said feedback clock from one of said plurality of distribution structures in said first mode, wherein said feedback path operates in said second mode when the distribution structure from which said feedback path selects said feedback clock is disabled.
Claim 14
Dependent Claim
50 words
The integrated circuit device as recited in claim 11, wherein said feedback path operates in said second mode when power is initially applied to the integrated circuit device and wherein select ones of said plurality of distribution structures are enabled sequentially as power is applied to the integrated circuit device.
Claim 15
Dependent Claim
18 words
The integrated circuit device as recited in claim 1, wherein said clock generator comprises a phase locked loop.
Claim 16
Dependent Claim
25 words
The integrated circuit device of claim 1, further comprising a microprocessor core, wherein said clock distribution path distributes said clock signal to said microprocessor core.
Claim 17
Dependent Claim
30 words
The integrated circuit device as recited in claim 15, wherein said external clock comprises a bus clock from a computer system bus to which the integrated circuit device is coupled.
Claim 18
Dependent Claim
73 words
A clock source, comprising a clock generator configured to produce a clock signal responsive to an external clock and responsive to a feedback clock; and a delay locked loop path and a distribution path having substantially similar delay characteristics, wherein said delay locked loop path and said distribution path each receive said clock signal, and wherein said feedback clock is selectively provided by either said delay locked loop path or said distribution path.
Claim 19
Dependent Claim
73 words
A clock source, comprising a clock generator configured to produce a clock signal responsive to an external clock and responsive to a feedback clock; and a delay locked loop path and a distribution path having substantially similar delay characteristics, wherein said delay locked loop path and said distribution path each receive said clock signal, and wherein said feedback clock is selectively provided by either said delay locked loop path or said distribution path.
Claim 20
Dependent Claim
29 words
The clock source as recited in claim 17, wherein said delay locked loop path is selected to provide said feedback clock during times when said distribution path is disabled.
Claim 21
Dependent Claim
50 words
The clock source as recited in claim 17, wherein said delay locked loop path is configured to compare a clock signal as outputted from a distribution path to said clock signal as outputted from said delay locked loop path and responsively adjust the delay of said delay locked loop path.
Claim 22
Dependent Claim
107 words
A clock distribution method, comprising generating a clock signal from an external clock; distributing said clock signal in an integrated circuit device to provide an internal clock; delaying said clock signal to provide a matching clock, wherein the delay of said matching clock from said clock signal substantially matches the delay of said internal clock from said clock signal, wherein said delaying comprises comparing said matching clock to said internal clock and adjusting the delay of said matching clock to approximately match the delay of said internal clock; and selecting between said internal clock and said matching clock to use in phase locking to said external clock.
Claim 23
Dependent Claim
107 words
A clock distribution method, comprising generating a clock signal from an external clock; distributing said clock signal in an integrated circuit device to provide an internal clock; delaying said clock signal to provide a matching clock, wherein the delay of said matching clock from said clock signal substantially matches the delay of said internal clock from said clock signal, wherein said delaying comprises comparing said matching clock to said internal clock and adjusting the delay of said matching clock to approximately match the delay of said internal clock; and selecting between said internal clock and said matching clock to use in phase locking to said external clock.
Claim 24
Dependent Claim
27 words
The clock distribution method as recited in claim 20, further comprising disabling said internal clock, wherein during said disabling said matching clock is selected by said selecting.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-01-10 | 2003-07-12 | 2004-01-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-01-10 | 2007-07-12 | 2008-01-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-01-10 | 2011-07-12 | 2012-01-11 | $7700.00 | Window Closed / Lapsed |