Synchronous mirror delay (SMD) circuit and method including a ring oscillator for timing coarse and fine delay intervals

Claim 3

The method of claim 1 wherein counting the number of clock cycles in response to the start signal comprises incrementing a delay count responsive to the counting clock signal in response to an Nth transition of the applied clock signal and terminating the counting responsive to an N+1th transition of the applied clock signal.

Claim 4

The method of claim 2 wherein counting the same number of clock cycles responsive to a transition of the reference counting clock signal comprises decrementing the delay count responsive to the counting clock signal until delay count is equal to the value at the time counting was initiated in response to the start signal.

Claim 5

The method of claim 1 further storing states of the counting clock signals and calculating a digital-to-time fine delay from the stored states of the counting clock signals according to a first methodology responsive to a selected one of the counting clock signals having a first logic state.

Claim 6

The method of claim 4 wherein calculating the digital-to-time fine delay from the stored states of the counting clock signals comprises calculating the fine delay according to a second methodology responsive to a selected one of the counting clock signals having a second logic state.

Claim 7

The method of claim 1 , further comprising storing the instantaneous states of the counting clock signals, and thereafter performing an XOR operation on adjacent pairs of clock signals to generate a plurality of fine delay control signals, with the fine delay control signal having a false value indicating the location of the reference counting clock signal edge at the point in time when the counting of the number of clock cycles ceases.

Claim 10

The method of claim 7 wherein measuring the coarse delay time comprises timing a digital-to-time coarse delay time in response to transitions of the reference oscillator clock signal after the first time.

Claim 11

The method of claim 7 wherein storing the state of the oscillator clock signals at a first time comprises storing the instantaneous states of the oscillator clock signals, and thereafter performing an XOR operation on adjacent pairs of clock signals to generate a plurality of fine delay control signals, with the fine delay control signal having a false value indicating the location of the reference oscillator clock signal edge at the first time.

Claim 12

The method of claim 7 wherein a first circuit generates the plurality of oscillator clocks signals, times the coarse delay time, and calculates the fine delay time, and wherein a second circuit replays the coarse delay time and generates the delayed clock signal.

Claim 13

The method of claim 10 wherein the first and second circuits are different circuits.

Claim 14

A clock synchronizing circuit, comprising: a ring oscillator operable to generate a plurality of tap clock signals with one tap clock signal being designated an oscillator clock signal in response to receiving a model delay signal, each tap clock signal having a respective delay relative to the oscillator clock signal; a delay circuit coupled to the ring oscillator and having an input to which an input clock signal is applied and operable to generate the model delay signal in response to the input clock signal having a delay relative to the input clock signal; a delay measuring circuit having a first measuring circuit coupled to the ring oscillator to receive the oscillator clock signal, the first measuring circuit operable to generate a first digital measurement signal indicative of a count value of the number of cycles of the oscillator clock signal between the model delay signal and the input clock signal, and further having a second measuring circuit coupled to the ring oscillator to receive the tap clock signals and operable to latch the tap clock signals responsive to the input clock signal to generate a second digital measurement signal; and at least one replay circuit having a first replay circuit coupled to the ring oscillator, the delay circuit, and the first measuring circuit, and further having a second replay circuit coupled to the ring oscillator, the second measuring circuit, and the first replay circuit, the first replay circuit operable to store the first digital measurement signal and further operable to generate a cycle count based on the oscillator clock signal and generate a first replay signal responsive to the cycle count being equal to the stored digital delay measurement signal, and the second replay circuit operable to generate a delayed clock signal responsive to the first replay signal and a first clock edge of one of the tap clock signals selected in accordance with the second measurement signal.

Claim 15

A clock synchronizing circuit, comprising: a ring oscillator operable to generate a plurality of tap clock signals with one tap clock signal being designated an oscillator clock signal in response to receiving a model delay signal, each tap clock signal having a respective delay relative to the oscillator clock signal; a delay circuit coupled to the ring oscillator and having an input to which an input clock signal is applied and operable to generate the model delay signal in response to the input clock signal having a delay relative to the input clock signal; a delay measuring circuit having a first measuring circuit coupled to the ring oscillator to receive the oscillator clock signal, the first measuring circuit operable to generate a first digital measurement signal indicative of a count value of the number of cycles of the oscillator clock signal between the model delay signal and the input clock signal, and further having a second measuring circuit coupled to the ring oscillator to receive the tap clock signals and operable to latch the tap clock signals responsive to the input clock signal to generate a second digital measurement signal; and at least one replay circuit having a first replay circuit coupled to the ring oscillator, the delay circuit, and the first measuring circuit, and further having a second replay circuit coupled to the ring oscillator, the second measuring circuit, and the first replay circuit, the first replay circuit operable to store the first digital measurement signal and further operable to generate a cycle count based on the oscillator clock signal and generate a first replay signal responsive to the cycle count being equal to the stored digital delay measurement signal, and the second replay circuit operable to generate a delayed clock signal responsive to the first replay signal and a first clock edge of one of the tap clock signals selected in accordance with the second measurement signal.

Claim 16

The clock synchronizing circuit of claim 12 wherein the second replay circuit comprises: a multiplexer having a plurality of inputs coupled to the ring oscillator, each input receiving a respective tap clock signal, the multiplexer operable to provide a respective tap clock signal on an output responsive to a plurality of input selection signals, the tap clock signal on the output corresponding to the delayed clock signal; a latch and compare circuit coupled to the ring oscillator, the latch and compare circuit operable to latch the tap clock signals responsive to the input clock signal and to generate a plurality of delay signals responsive to the latched tap clock signals; and a delay transform circuit coupled to receive the first digital measurement signal and coupled to the latch and compare circuit and the multiplexer, the delay transform circuit operable in response to the delay signals to select a respective input selection signal and to activate the selected input selection signal responsive to the first replay signal going active.

Claim 17

The clock synchronizing circuit of claim 13 wherein the multiplexer comprises a plurality of transmission gates.

Claim 18

The clock synchronizing circuit of claim 13 wherein the ring oscillator includes N delay stages that generate tap clock signals T 1 -TN, respectively, and the latch and compare circuit latches tap clock signals T 1 -TN from the ring oscillator and performs an XOR operation on each pair of latched tap clock signals T 1 -T 2 , T 2 -T 3 , and so on through TN- 1 -TN, and also performs an XOR operation on the pair T 1 and TN, with each XOR operation generating a corresponding delay signal.

Claim 19

The clock synchronizing circuit of claim 15 wherein the delay transform circuit operates in a first mode responsive to a selected one of the tap clock signals T 1 -TN having a first logic state.

Claim 20

The clock synchronizing circuit of claim 16 wherein the delay transform circuit operates in a second mode responsive to a selected one of the tap clock signals T 1 -TN having a second logic state.

Claim 21

The clock synchronizing circuit of claim 12 wherein the first measuring circuit and the first replay circuit share a circuit comprising: an up/down counter coupled to receive the input clock signal and the model delay signal, and coupled to the ring oscillator to receive the oscillator clock signal, the up/down counter operable responsive to a transition of the model delay signal to increment the count value from a reference count value responsive to the oscillator clock signal, and operable responsive to a transition of the input clock signal to decrement the count value responsive to the oscillator clock signal; and a comparator coupled to the up/down counter, the comparator activating the first digital measurement signal responsive to the count value being equal to the reference count value.

Claim 22

The clock synchronizing circuit of claim 12 wherein the at least one replay circuit comprises first, second, third, and fourth replay circuits coupled to the measuring circuit.

Claim 23

A clock synchronizing circuit for generating a delayed clock signal in response to an input clock signal, the synchronizing circuit comprising: a ring oscillator operable to generate a plurality of tap clock signals with one tap clock signal being designated an oscillator clock signal in response to receiving a ring oscillator start signal, each tap clock signal having a respective delay relative to the oscillator clock signal; a coarse delay measuring circuit coupled to the ring oscillator to receive the oscillator clock signal, the coarse delay measuring circuit operable to generate a coarse digital delay measurement signal indicative of a count value of the oscillator clock signal between the ring oscillator start signal and the input clock signal; a fine delay measuring circuit coupled to the ring oscillator to receive the tap clock signals and operable to latch the tap clock signals responsive to the input clock signal to generate a fine digital delay measurement signal; a coarse delay replay circuit coupled to the ring oscillator and coarse delay measuring circuit, the coarse delay replay circuit operable to store the coarse digital delay measurement signal and further operable to generate a cycle count based on the oscillator clock signal and generate a coarse delay replay signal responsive to the cycle count being equal to the stored digital delay measurement signal, a fine delay replay circuit coupled to the ring oscillator, the fine delay measuring circuit, and the coarse delay replay circuit, the fine delay replay circuit operable to generate a fine delay replay signal responsive to the coarse delay replay signal and a first clock edge of one of the tap clock signals selected in accordance with the fine delay measurement signal; and an output circuit coupled to the coarse and fine delay replay circuits and operable to generate the delayed clock signal responsive to the coarse delay replay signal and the fine delay replay signal.

Claim 24

A clock synchronizing circuit for generating a delayed clock signal in response to an input clock signal, the synchronizing circuit comprising: a ring oscillator operable to generate a plurality of tap clock signals with one tap clock signal being designated an oscillator clock signal in response to receiving a ring oscillator start signal, each tap clock signal having a respective delay relative to the oscillator clock signal; a coarse delay measuring circuit coupled to the ring oscillator to receive the oscillator clock signal, the coarse delay measuring circuit operable to generate a coarse digital delay measurement signal indicative of a count value of the oscillator clock signal between the ring oscillator start signal and the input clock signal; a fine delay measuring circuit coupled to the ring oscillator to receive the tap clock signals and operable to latch the tap clock signals responsive to the input clock signal to generate a fine digital delay measurement signal; a coarse delay replay circuit coupled to the ring oscillator and coarse delay measuring circuit, the coarse delay replay circuit operable to store the coarse digital delay measurement signal and further operable to generate a cycle count based on the oscillator clock signal and generate a coarse delay replay signal responsive to the cycle count being equal to the stored digital delay measurement signal, a fine delay replay circuit coupled to the ring oscillator, the fine delay measuring circuit, and the coarse delay replay circuit, the fine delay replay circuit operable to generate a fine delay replay signal responsive to the coarse delay replay signal and a first clock edge of one of the tap clock signals selected in accordance with the fine delay measurement signal; and an output circuit coupled to the coarse and fine delay replay circuits and operable to generate the delayed clock signal responsive to the coarse delay replay signal and the fine delay replay signal.

Claim 25

The clock synchronizing circuit of claim 20 wherein the output circuit comprises an AND gate.

Claim 26

The clock synchronizing circuit of claim 20 wherein the coarse delay measuring circuit comprises a counter circuit coupled to receive the ring oscillator start signal and coupled to the ring oscillator to receive the oscillator clock signal, the counter circuit operable responsive to a transition of the oscillator start signal to increment the count value from a reference count value responsive to the oscillator clock signal.

Claim 27

The clock synchronizing circuit of claim 20 wherein the coarse delay replay circuit comprises a counter circuit coupled to receive the input clock signal and coupled to the ring oscillator to receive the oscillator clock signal, the counter circuit operable responsive to a transition of the input clock signal to decrement the count value responsive to the oscillator clock signal.

Claim 28

The clock synchronizing circuit of claim 20 wherein the fine delay measuring circuit and the fine delay replay circuit share a fine delay circuit comprising: a multiplexer having a plurality of inputs coupled to the ring oscillator, each input receiving a respective tap clock signal, the multiplexer operable to provide a respective tap clock signal on an output responsive to a plurality of input selection signals, with the tap clock signal on the output corresponding to the fine delay replay signal; a latch and compare circuit coupled to the ring oscillator, the latch and compare circuit operable to latch the tap clock signals responsive to the input clock signal and to generate a plurality of fine delay signals responsive to the latched tap clock signals; and a fine delay transform circuit coupled to receive the coarse delay enable signal and coupled to the latch and compare circuit and the multiplexer, the fine delay transform circuit operable in response to the fine delay signals to select a respective input selection signal and to activate the selected input selection signal responsive to the coarse delay replay signal going active.

Claim 29

The clock synchronizing circuit of claim 24 wherein the multiplexer comprises a plurality of transmission gates.

Claim 30

The clock synchronizing circuit of claim 24 wherein the ring oscillator includes N delay stages that generate tap clock signals T 1 -TN, respectively, and the latch and compare circuit latches tap clock signals T 1 -TN from the ring oscillator and performs an XOR operation on each pair of latched tap clock signals T 1 -T 2 , T 2 -T 3 , and so on through TN- 1 -TN, and also performs an XOR operation on the pair T 1 and TN, with each XOR operation generating a corresponding fine delay signal.

Claim 31

The clock synchronizing circuit of claim 26 wherein the fine delay transform circuit operates in a first mode responsive to a selected one of the tap clock signals T 1 -TN having a first logic state.

Claim 32

The clock synchronizing circuit of claim 27 wherein the fine delay transform circuit operates in a second mode responsive to a selected one of the tap clock signals T 1 -TN having a second logic state.

Claim 33

A memory device, comprising: an address bus; a control bus; a data bus; an address decoder coupled to the address bus; a read/write circuit coupled to the data bus; a control circuit coupled to the control bus; a memory-cell array coupled to the address decoder, control circuit, and read/write circuit; and a clock synchronizing circuit coupled to at least the control circuit and adapted to receive an input clock signal, the clock synchronizing circuit operable to generate a delayed clock signal and the control circuit generating control signals in response to the delayed clock signal, the clock synchronizing circuit comprising, a ring oscillator operable to generate a plurality of tap clock signals with one tap clock signal being designated an oscillator clock signal in response to receiving a model delay signal, each tap clock signal having a respective delay relative to the oscillator clock signal; a delay circuit coupled to the ring oscillator and having an input to which an input clock signal is applied and operable to generate the model delay signal in response to the input clock signal having a delay relative to the input clock signal; a delay measuring circuit having a first measuring circuit coupled to the ring oscillator to receive the oscillator clock signal, the first measuring circuit operable to generate a first digital measurement signal indicative of a count value of the number of cycles of the oscillator clock signal between the model delay signal and the input clock signal, and further having a second measuring circuit coupled to the ring oscillator to receive the tap clock signals and operable to latch the tap clock signals responsive to the input clock signal to generate a second digital measurement signal; and at least one replay circuit having a first replay circuit coupled to the ring oscillator, the delay circuit, and the first measuring circuit, and further having a second replay circuit coupled to the ring oscillator, the second measuring circuit, and the first replay circuit, the first replay circuit operable to store the first digital measurement signal and further operable to generate a cycle count based on the oscillator clock signal and generate a first replay signal responsive to the cycle count being equal to the stored digital delay measurement signal, and the second replay circuit operable to generate a delayed clock signal responsive to the first replay signal and a first clock edge of one of the tap clock signals selected in accordance with the second measurement signal.

Claim 34

A memory device, comprising: an address bus; a control bus; a data bus; an address decoder coupled to the address bus; a read/write circuit coupled to the data bus; a control circuit coupled to the control bus; a memory-cell array coupled to the address decoder, control circuit, and read/write circuit; and a clock synchronizing circuit coupled to at least the control circuit and adapted to receive an input clock signal, the clock synchronizing circuit operable to generate a delayed clock signal and the control circuit generating control signals in response to the delayed clock signal, the clock synchronizing circuit comprising, a ring oscillator operable to generate a plurality of tap clock signals with one tap clock signal being designated an oscillator clock signal in response to receiving a model delay signal, each tap clock signal having a respective delay relative to the oscillator clock signal; a delay circuit coupled to the ring oscillator and having an input to which an input clock signal is applied and operable to generate the model delay signal in response to the input clock signal having a delay relative to the input clock signal; a delay measuring circuit having a first measuring circuit coupled to the ring oscillator to receive the oscillator clock signal, the first measuring circuit operable to generate a first digital measurement signal indicative of a count value of the number of cycles of the oscillator clock signal between the model delay signal and the input clock signal, and further having a second measuring circuit coupled to the ring oscillator to receive the tap clock signals and operable to latch the tap clock signals responsive to the input clock signal to generate a second digital measurement signal; and at least one replay circuit having a first replay circuit coupled to the ring oscillator, the delay circuit, and the first measuring circuit, and further having a second replay circuit coupled to the ring oscillator, the second measuring circuit, and the first replay circuit, the first replay circuit operable to store the first digital measurement signal and further operable to generate a cycle count based on the oscillator clock signal and generate a first replay signal responsive to the cycle count being equal to the stored digital delay measurement signal, and the second replay circuit operable to generate a delayed clock signal responsive to the first replay signal and a first clock edge of one of the tap clock signals selected in accordance with the second measurement signal.

Claim 35

The memory device of claim 29 wherein the second replay circuit of the clock synchronizing circuit comprises: a multiplexer having a plurality of inputs coupled to the ring oscillator, each input receiving a respective tap clock signal, the multiplexer operable to provide a respective tap clock signal on an output responsive to a plurality of input selection signals, the tap clock signal on the output corresponding to the delayed clock signal; a latch and compare circuit coupled to the ring oscillator, the latch and compare circuit operable to latch the tap clock signals responsive to the input clock signal and to generate a plurality of delay signals responsive to the latched tap clock signals; and a delay transform circuit coupled to receive the first digital measurement signal and coupled to the latch and compare circuit and the multiplexer, the delay transform circuit operable in response to the delay signals to select a respective input selection signal and to activate the selected input selection signal responsive to the first replay signal going active.

Claim 36

The memory device of claim 30 wherein the multiplexer comprises a plurality of transmission gates.

Claim 37

The memory device of claim 30 wherein the ring oscillator includes N delay stages that generate tap clock signals T 1 -TN, respectively, and the latch and compare circuit latches tap clock signals T 1 -TN from the ring oscillator and performs an XOR operation on each pair of latched tap clock signals T 1 -T 2 , T 2 -T 3 , and so on through TN- 1 -TN, and also performs an XOR operation on the pair T 1 and TN, with each XOR operation generating a corresponding delay signal.

Claim 38

The memory device of claim 32 wherein the delay transform circuit operates in a first mode responsive to a selected one of the tap clock signals T 1 -TN having a first logic state.

Claim 39

The memory device of claim 33 wherein the delay transform circuit operates in a second mode responsive to a selected one of the tap clock signals T 1 -TN having a second logic state.

Claim 40

The memory device of claim 29 wherein the first measuring circuit and the first replay circuit of the clock synchronizing circuit share a circuit comprising: an up/down counter coupled to receive the input clock signal and the model delay signal, and coupled to the ring oscillator to receive the oscillator clock signal, the up/down counter operable responsive to a transition of the model delay signal to increment the count value from a reference count value responsive to the oscillator clock signal, and operable responsive to a transition of the input clock signal to decrement the count value responsive to the oscillator clock signal; and a comparator coupled to the up/down counter, the comparator activating the first digital measurement signal responsive to the count value being equal to the reference count value.

Claim 41

The memory device of claim 29 wherein the at least one replay circuit of the clock synchronizing circuit comprises first, second, third, and fourth replay circuits coupled to the measuring circuit.

Claim 42

A memory device, comprising: an address bus; a control bus; a data bus; an address decoder coupled to the address bus; a read/write circuit coupled to the data bus; a control circuit coupled to the control bus; a memory-cell array coupled to the address decoder, control circuit, and read/write circuit; and a clock synchronizing circuit coupled to at least the control circuit and adapted to receive an input clock signal, the clock synchronizing circuit operable to generate a delayed clock signal and the control circuit generating control signals in response to the delayed clock signal, the clock synchronizing circuit comprising, a ring oscillator operable to generate a plurality of tap clock signals with one tap clock signal being designated an oscillator clock signal in response to receiving a ring oscillator start signal, each tap clock signal having a respective delay relative to the oscillator clock signal; a coarse delay measuring circuit coupled to the ring oscillator to receive the oscillator clock signal, the coarse delay measuring circuit operable to generate a coarse digital delay measurement signal indicative of a count value of the oscillator clock signal between the ring oscillator start signal and the input clock signal; a fine delay measuring circuit coupled to the ring oscillator to receive the tap clock signals and operable to latch the tap clock signals responsive to the input clock signal to generate a fine digital delay measurement signal; a coarse delay replay circuit coupled to the ring oscillator and coarse delay measuring circuit, the coarse delay replay circuit operable to store the coarse digital delay measurement signal and further operable to generate a cycle count based on the oscillator clock signal and generate a coarse delay replay signal responsive to the cycle count being equal to the stored digital delay measurement signal, a fine delay replay circuit coupled to the ring oscillator, the fine delay measuring circuit, and the coarse delay replay circuit, the fine delay replay circuit operable to generate a fine delay replay signal responsive to the coarse delay replay signal and a first clock edge of one of the tap clock signals selected in accordance with the fine delay measurement signal; and an output circuit coupled to the coarse and fine delay replay circuits and operable to generate the delayed clock signal responsive to the coarse delay replay signal and the fine delay replay signal.

Claim 43

A memory device, comprising: an address bus; a control bus; a data bus; an address decoder coupled to the address bus; a read/write circuit coupled to the data bus; a control circuit coupled to the control bus; a memory-cell array coupled to the address decoder, control circuit, and read/write circuit; and a clock synchronizing circuit coupled to at least the control circuit and adapted to receive an input clock signal, the clock synchronizing circuit operable to generate a delayed clock signal and the control circuit generating control signals in response to the delayed clock signal, the clock synchronizing circuit comprising, a ring oscillator operable to generate a plurality of tap clock signals with one tap clock signal being designated an oscillator clock signal in response to receiving a ring oscillator start signal, each tap clock signal having a respective delay relative to the oscillator clock signal; a coarse delay measuring circuit coupled to the ring oscillator to receive the oscillator clock signal, the coarse delay measuring circuit operable to generate a coarse digital delay measurement signal indicative of a count value of the oscillator clock signal between the ring oscillator start signal and the input clock signal; a fine delay measuring circuit coupled to the ring oscillator to receive the tap clock signals and operable to latch the tap clock signals responsive to the input clock signal to generate a fine digital delay measurement signal; a coarse delay replay circuit coupled to the ring oscillator and coarse delay measuring circuit, the coarse delay replay circuit operable to store the coarse digital delay measurement signal and further operable to generate a cycle count based on the oscillator clock signal and generate a coarse delay replay signal responsive to the cycle count being equal to the stored digital delay measurement signal, a fine delay replay circuit coupled to the ring oscillator, the fine delay measuring circuit, and the coarse delay replay circuit, the fine delay replay circuit operable to generate a fine delay replay signal responsive to the coarse delay replay signal and a first clock edge of one of the tap clock signals selected in accordance with the fine delay measurement signal; and an output circuit coupled to the coarse and fine delay replay circuits and operable to generate the delayed clock signal responsive to the coarse delay replay signal and the fine delay replay signal.

Claim 44

The memory device of claim 37 wherein the output circuit of the clock synchronizing circuit comprises an AND gate.

Claim 45

The memory device of claim 37 wherein the coarse delay measuring circuit of the clock synchronizing circuit comprises a counter circuit coupled to receive the ring oscillator start signal and coupled to the ring oscillator to receive the oscillator clock signal, the counter circuit operable responsive to a transition of the oscillator start signal to increment the count value from a reference count value responsive to the oscillator clock signal.

Claim 46

The memory device of claim 37 Wherein the coarse delay replay circuit of the clock synchronizing circuit comprises a counter circuit coupled to receive the input clock signal and coupled to the ring oscillator to receive the oscillator clock signal, the counter circuit operable responsive to a transition of the input clock signal to decrement the count value responsive to the oscillator clock signal.

Claim 47

The memory device of claim 37 wherein the fine delay measuring circuit and the fine delay replay circuit of the clock synchronizing circuit share a fine delay circuit comprising: a multiplexer having a plurality of inputs coupled to the ring oscillator, each input receiving a respective tap clock signal, the multiplexer operable to provide a respective tap clock signal on an output responsive to a plurality of input selection signals, with the tap clock signal on the output corresponding to the fine delay replay signal; a latch and compare circuit coupled to the ring oscillator, the latch and compare circuit operable to latch the tap clock signals responsive to the input clock signal and to generate a plurality of fine delay signals responsive to the latched tap clock signals; and a fine delay transform circuit coupled to receive the coarse delay enable signal and coupled to the latch and compare circuit and the multiplexer, the fine delay transform circuit operable in response to the fine delay signals to select a respective input selection signal and to activate the selected input selection signal responsive to the coarse delay replay signal going active.

Claim 48

The memory device of claim 41 wherein the multiplexer comprises a plurality of transmission gates.

Claim 49

The memory device of claim 41 wherein the ring oscillator includes N delay stages that generate tap clock signals T 1 -TN, respectively, and the latch and compare circuit latches tap clock signals T 1 -TN from the ring oscillator and performs an XOR operation on each pair of latched tap clock signals T 1 -T 2 , T 2 -T 3 , and so on through TN- 1 -TN, and also performs an XOR operation on the pair T 1 and TN, with each XOR operation generating a corresponding fine delay signal.

Claim 50

The memory device of claim 43 wherein the fine delay transform circuit operates in a first mode responsive to a selected one of the tap clock signals T 1 -TN having a first logic state.

Claim 51

The memory device of claim 44 wherein the fine delay transform circuit operates in a second mode responsive to a selected one of the tap clock signals T 1 -TN having a second logic state.