USRE38482E1 — Delay stage circuitry for a ring oscillator

Claim 1

Independent Claim 187 words

A ring oscillator comprising: a plurality of ring coupled delay stages, each delay stage comprising: (A) a differential amplifier for generating a differential output signal comprising a first output signal at a first node and a second output signal at a second node, wherein the differential amplifier further comprises: (i) a first transistor coupled to the first node; (ii) a second transistor coupled to the second node and the first transistor, wherein the first and second transistors are biased by an output level biasing voltage; (iii) a third transistor coupled to the first node, wherein the third transistor receives a first input signal from a preceding delay stage; (iv) a fourth transistor coupled to the second node and the third transistor, wherein the fourth transistor receives a second input signal from the preceding delay stage; (B) a self-biased voltage clamping circuit coupled to the first and second nodes to limit a peak-to-peak voltage swing of the differential output signal; and (C) a current source coupled to the differential amplifier, the current source varying a bias current through the current source in accordance with a delay bias voltage.

Claim 2

Dependent Claim 187 words

A ring oscillator comprising: a plurality of ring coupled delay stages, each delay stage comprising: (A) a differential amplifier for generating a differential output signal comprising a first output signal at a first node and a second output signal at a second node, wherein the differential amplifier further comprises: (i) a first transistor coupled to the first node; (ii) a second transistor coupled to the second node and the first transistor, wherein the first and second transistors are biased by an output level biasing voltage; (iii) a third transistor coupled to the first node, wherein the third transistor receives a first input signal from a preceding delay stage; (iv) a fourth transistor coupled to the second node and the third transistor, wherein the fourth transistor receives a second input signal from the preceding delay stage; (B) a self-biased voltage clamping circuit coupled to the first and second nodes to limit a peak-to-peak voltage swing of the differential output signal; and (C) a current source coupled to the differential amplifier, the current source varying a bias current through the current source in accordance with a delay bias voltage.

Claim 3

Dependent Claim 40 words

The ring oscillator of claim 1 , wherein the voltage clamping circuit further comprises: (i) a first diode-coupled transistor; and (ii) a second diode-coupled transistor, wherein the first and second diode-coupled transistors are cross-coupled between the first and second nodes.

Claim 4

Dependent Claim 18 words

The ring oscillator of claim 2 , wherein the first and second diode-coupled transistor are metal-oxide semiconductor transistors.

Claim 5

Dependent Claim 17 words

The ring oscillator of claim 2 , wherein the first and second diode-coupled transistors are N-type transistors.

Claim 6

Dependent Claim 16 words

The ring oscillator of claim 1 , wherein the current source further comprises a fifth transistor.

Claim 7

Dependent Claim 28 words

The ring oscillator of claim 1 wherein the first and second transistors are of a first type, wherein the third and fourth transistors are of a second type.

Claim 8

Dependent Claim 22 words

The ring oscillator of claim 6 wherein the first and second transistors are P-type and the third and fourth transistors are N-type.

Claim 9

Dependent Claim 22 words

The ring oscillator of claim 6 wherein the first and second transistors are N-type and the third and fourth transistors are P-type.

Claim 10

Dependent Claim 14 words

The ring oscillator of claim 6 wherein the first and second types are complementary.

Claim 11

Dependent Claim 16 words

The ring oscillator of claim 1 wherein each delay stage further comprises a source follower buffer.

Claim 12

Dependent Claim 206 words

A ring oscillator comprising: a plurality of ring coupled delay stages, each delay stage comprising: (A) a differential amplifier for generating a first output signal at a first node and a second output signal at a second node, wherein the differential amplifier further comprises: (i) a first transistor coupled between the first node and a first potential; (ii) a second transistor coupled between the second node and the first potential, wherein the first and second transistors are biased by an output level biasing voltage; (iii) a third transistor coupled between the first node and a third node, wherein the third transistor receives a first input signal from a preceding delay stage; (iv) a fourth transistor coupled between the second node and the third node, wherein the fourth transistor receives a second input signal from the preceding delay stage; (B) a current source coupled between the third node and a second potential, the current source varying a bias current through the current source in accordance with a delay bias voltage; and (C) a voltage clamping circuit coupled to the first and second nodes to limit a relative peak-to-peak voltage swing of the first and second output signals without independently clamping each of the first and second nodes.

Claim 13

Dependent Claim 206 words

A ring oscillator comprising: a plurality of ring coupled delay stages, each delay stage comprising: (A) a differential amplifier for generating a first output signal at a first node and a second output signal at a second node, wherein the differential amplifier further comprises: (i) a first transistor coupled between the first node and a first potential; (ii) a second transistor coupled between the second node and the first potential, wherein the first and second transistors are biased by an output level biasing voltage; (iii) a third transistor coupled between the first node and a third node, wherein the third transistor receives a first input signal from a preceding delay stage; (iv) a fourth transistor coupled between the second node and the third node, wherein the fourth transistor receives a second input signal from the preceding delay stage; (B) a current source coupled between the third node and a second potential, the current source varying a bias current through the current source in accordance with a delay bias voltage; and (C) a voltage clamping circuit coupled to the first and second nodes to limit a relative peak-to-peak voltage swing of the first and second output signals without independently clamping each of the first and second nodes.

Claim 14

Dependent Claim 40 words

The ring oscillator of claim 11 , wherein the voltage clamping circuit further comprises: (i) a first diode-coupled transistor; and (ii) a second diode-coupled transistor, wherein the first and second diode-coupled transistors are cross-coupled between the first and second nodes.

Claim 15

Dependent Claim 18 words

The ring oscillator of claim 12 , wherein the first and second diode-coupled transistors are metal-oxide semiconductor transistors.

Claim 16

Dependent Claim 17 words

The ring oscillator of claim 12 , wherein the first and second diode-coupled transistors are N-type transistors.

Claim 17

Dependent Claim 16 words

The ring oscillator of claim 11 , wherein the current source further comprises a fifth transistor.

Claim 18

Dependent Claim 28 words

The ring oscillator of claim 11 wherein the first and second transistors are of a first type, wherein the third and fourth transistors are of a second type.

Claim 19

Dependent Claim 22 words

The ring oscillator of claim 16 wherein the first and second transistors are P-type and the third and fourth transistors are N-type.

Claim 20

Dependent Claim 22 words

The ring oscillator of claim 16 wherein the first and second transistors are N-type and the third and fourth transistors are P-type.

Claim 21

Dependent Claim 14 words

The ring oscillator of claim 16 wherein the first and second types are complementary.

Claim 22

Dependent Claim 16 words

The ring oscillator of claim 11 wherein each delay stage further comprises a source follower buffer.

Claim 23

Dependent Claim 67 words

A ring oscillator comprising: a plurality of ring coupled delay stages, each delay stage comprising: a differential amplifier providing a differential output signal; a self-biased voltage clamping circuit coupled to limit a peak-to-peak voltage swing of the differential output signal; and a current source coupled to the differential amplifier, the current source varying a bias current through the current source in accordance with a delay bias voltage.

Claim 24

Dependent Claim 67 words

A ring oscillator comprising: a plurality of ring coupled delay stages, each delay stage comprising: a differential amplifier providing a differential output signal; a self-biased voltage clamping circuit coupled to limit a peak-to-peak voltage swing of the differential output signal; and a current source coupled to the differential amplifier, the current source varying a bias current through the current source in accordance with a delay bias voltage.

Claim 25

Dependent Claim 73 words

The ring oscillator of claim 21 , wherein the differential amplifier provides a first output signal at a first node and a second output signal at a second node, the first and second output signal forming the differential output signal, wherein the voltage clamping circuit further comprises: (i) a first diode-coupled transistor; and (ii) a second diode-coupled transistor, wherein the first and second diode-coupled transistors are cross-coupled between the first and second nodes.

Claim 26

Dependent Claim 100 words

A ring oscillator comprising: a plurality of ring coupled delay stages, each delay stage comprising: a differential amplifier providing a differential output signal comprising a first output signal at a first node and a second output signal at a second node; a voltage clamping circuit coupled to the first and second nodes to limit a peak-to-peak voltage swing of the differential output signal without independently clamping each of the first and second nodes; and a current source coupled to the differential amplifier, the current source varying a bias current through the current source in accordance with a delay bias voltage.

Claim 27

Dependent Claim 100 words

A ring oscillator comprising: a plurality of ring coupled delay stages, each delay stage comprising: a differential amplifier providing a differential output signal comprising a first output signal at a first node and a second output signal at a second node; a voltage clamping circuit coupled to the first and second nodes to limit a peak-to-peak voltage swing of the differential output signal without independently clamping each of the first and second nodes; and a current source coupled to the differential amplifier, the current source varying a bias current through the current source in accordance with a delay bias voltage.

Claim 28

Dependent Claim 40 words

The ring oscillator of claim 23 , wherein the voltage clamping circuit further comprises: (i) a first diode-coupled transistor; and (ii) a second diode-coupled transistor, wherein the first and second diode-coupled transistors are cross-coupled between the first and second nodes.

Claim 29

Dependent Claim 118 words

A synchronous memory device comprising: an array of memory cells to store data; a clock synchronization loop to generate a plurality of clock signals, each clock signal having a timing relationship with respect to a reference clock signal; first interpolator circuitry to generate a first internal clock signal from a first and a second clock signal of the plurality of clock signals, wherein a phase of the first internal clock signal is interpolated from respective phases of the first and second clock signals according to phase information indicative of whether the first internal clock signal leads or lags a first external clock signal; and interface circuitry to synchronize a transmission of data with the first internal clock signal.

Claim 30

Dependent Claim 118 words

A synchronous memory device comprising: an array of memory cells to store data; a clock synchronization loop to generate a plurality of clock signals, each clock signal having a timing relationship with respect to a reference clock signal; first interpolator circuitry to generate a first internal clock signal from a first and a second clock signal of the plurality of clock signals, wherein a phase of the first internal clock signal is interpolated from respective phases of the first and second clock signals according to phase information indicative of whether the first internal clock signal leads or lags a first external clock signal; and interface circuitry to synchronize a transmission of data with the first internal clock signal.

Claim 31

Dependent Claim 17 words

The memory device of claim 25 wherein the clock synchronization loop is a phase locked loop circuit.

Claim 32

Dependent Claim 32 words

The memory device of claim 25 wherein the timing relationship of each one of the plurality of clock signals is a respective phase offset from a phase of the reference clock signal.

Claim 33

Dependent Claim 33 words

The memory device of claim 25 wherein the clock synchronization loop comprises a plurality of delay elements coupled in series, each delay element outputting at least one of the plurality of clock signals.

Claim 34

Dependent Claim 19 words

The memory device of claim 28 wherein the plurality of delay elements in an even number of delay elements.

Claim 35

Dependent Claim 30 words

The memory device of claim 25 further comprising selection circuitry, coupled to the clock synchronization loop, to select the first and second clock signals from the plurality of clock signals.

Claim 36

Dependent Claim 104 words

The memory device of claim 30 further comprising: a detector circuit to detect a phase polarity between the first internal clock signal and the first external clock signal; a shift register, coupled in parallel with the selection circuitry, to output selection signals that control selection of the first and second clock signals; and a control circuit to provide shift information to the shift register based on the phase polarity such that the selection signals output by the shift register select clock signals of the plurality of clock signals that have phases neighboring, on respective either sides, the phase of the first external clock signal.

Claim 37

Dependent Claim 69 words

The memory device of claim 25 , further comprising: a detector circuit, coupled to the first interpolator circuitry, to detect the phase information; and a control circuit to generate a control voltage that is responsive to the phase information, wherein the first interpolator circuitry steers the phase of the first internal clock signal between the phase of the first and second clock signals in response to the control voltage.

Claim 38

Dependent Claim 18 words

The memory device of claim 32 wherein after detection the phase information is represented by a binary value.

Claim 39

Dependent Claim 42 words

The memory device of claim 32 wherein the control circuit comprises: a digital counter to generate a digital count value in response to the phase information; and a digital to analog converter to generate the control voltage from the digital count value.

Claim 40

Dependent Claim 30 words

The memory device of claim 25 further comprising a buffer circuit to receive a second external clock signal and generate the reference clock signal using the second external clock signal.

Claim 41

Dependent Claim 19 words

The memory device of claim 35 wherein a reception of data is synchronized with the second external clock signal.

Claim 42

Dependent Claim 26 words

The memory device of claim 35 wherein the plurality of clock signals comprises a clock signal that is in phase with the second external clock signal.

Claim 43

Dependent Claim 70 words

The memory device of claim 25 further comprising second interpolator circuitry to generate a second internal clock signal from a pair of clock signals of the plurality of clock signals, wherein a phase of the second internal clock signal is interpolated from respective phases of the pair of clock signals according to phase information indicative of whether the second internal clock signal leads or lags a second external clock signal.

Claim 44

Dependent Claim 24 words

The memory device of claim 25 wherein the data is transmitted during a plurality of clock edge transitions of the first external clock signal.

Claim 45

Dependent Claim 139 words

An integrated circuit device comprising: interface circuitry to receive first and second external clock signals; and clock synchronization circuitry to synchronize a transmission of data with the first external clock signal and to synchronize a reception of data with the second external clock signal, the clock synchronization circuitry including: a reference loop to receive a reference clock signal and generate a plurality of clock signals, each clock signal of the plurality of clock signals having a predetermined timing relationship with the reference clock signal; a first subloop circuit, coupled to the reference loop, to synchronize the transmission of data with the first external clock signal using the plurality of clock signals; and a second subloop circuit, coupled to the reference loop, to synchronize the reception of data with the second external clock signal using the plurality of clock signals.

Claim 46

Dependent Claim 139 words

An integrated circuit device comprising: interface circuitry to receive first and second external clock signals; and clock synchronization circuitry to synchronize a transmission of data with the first external clock signal and to synchronize a reception of data with the second external clock signal, the clock synchronization circuitry including: a reference loop to receive a reference clock signal and generate a plurality of clock signals, each clock signal of the plurality of clock signals having a predetermined timing relationship with the reference clock signal; a first subloop circuit, coupled to the reference loop, to synchronize the transmission of data with the first external clock signal using the plurality of clock signals; and a second subloop circuit, coupled to the reference loop, to synchronize the reception of data with the second external clock signal using the plurality of clock signals.

Claim 47

Dependent Claim 30 words

The integrated circuit device of claim 40 wherein the first subloop circuit generates an internal transmit clock signal having a phase relationship with respect to the first external clock signal.

Claim 48

Dependent Claim 15 words

The integrated circuit device of claim 41 wherein the phase relationship is a quadrature relationship.

Claim 49

Dependent Claim 21 words

The integrated circuit device of claim 41 wherein the internal transmit clock is in phase with the first external clock signal.

Claim 50

Dependent Claim 110 words

The integrated circuit device of claim 40 wherein the first subloop circuit further comprises: selection circuitry to select first and second clock signals of the plurality of clock signals; interpolator circuitry to interpolate between the first and second clock signals, and to generate an internal transmit clock signal in response to a control signal, wherein the control signal steers the phase of the internal transmit clock signal between respective phases of the first and second clock signals; and detector circuitry to detect phase information indicative of whether the internal transmit clock signal leads or lags the first external clock signal, and to generate the control signal using the phase information.

Claim 51

Dependent Claim 30 words

The integrated circuit device of claim 40 wherein the second subloop circuit generates an internal receive clock signal having a phase relationship with respect to the second external clock signal.

Claim 52

Dependent Claim 22 words

The integrated circuit device of claim 45 wherein the internal receive clock signal is in phase with the second external clock signal.

Claim 53

Dependent Claim 110 words

The integrated circuit device of claim 40 wherein the second subloop circuit further comprises: selection circuitry to select first and second clock signals of the plurality of clock signals; interpolator circuitry to interpolate between the first and second clock signals, and to generate an internal receive clock signal in response to a control signal, wherein the control signal steers the phase of the internal receive clock signal between respective phases of the first and second clock signals; and detector circuitry to detect phase information indicative of whether the internal receive clock signal leads or lags the second external clock signal, and to generate the control signal using the phase information.

Claim 54

Dependent Claim 55 words

The integrated circuit device of claim 40 wherein a first clock signal of the plurality of clock signals is in phase with the second external clock signal, and the other clock signals of the plurality of clock signals have respective phases that are evenly spaced across a clock period of the second external clock signal.

Claim 55

Dependent Claim 17 words

The integrated circuit device of claim 40 wherein the reference loop is a phase locked loop circuit.

Claim 56

Dependent Claim 25 words

The integrated circuit device of claim 40 wherein the data is transmitted during a plurality of clock edge transitions of the first external clock signal.

Claim 57

Dependent Claim 32 words

The integrated circuit device of claim 40 further comprising a buffer circuit to receive the second external clock signal and to generate the reference clock signal from the second external clock signal.

Claim 58

Dependent Claim 146 words

A clock synchronization circuit comprising: a plurality of delay stages coupled in series to output a plurality of clock signals, each delay stage having a delay time with respect to a reference clock signal; interpolator circuitry to generate a first clock signal using a pair of clock signals of the plurality of clock signals, wherein a phase of the first clock signal is interpolated between respective phases of each clock signal of the pair of clock signals in accordance with information indicative of whether a phase of the first clock signal leads or lags a phase of an input clock signal; and a detector circuit to compare the phase of the first clock signal with the phase of the input clock signal, to generate the information indicative of whether the phase of the first clock signal leads or lags the phase of the input clock signal.

Claim 59

Dependent Claim 146 words

A clock synchronization circuit comprising: a plurality of delay stages coupled in series to output a plurality of clock signals, each delay stage having a delay time with respect to a reference clock signal; interpolator circuitry to generate a first clock signal using a pair of clock signals of the plurality of clock signals, wherein a phase of the first clock signal is interpolated between respective phases of each clock signal of the pair of clock signals in accordance with information indicative of whether a phase of the first clock signal leads or lags a phase of an input clock signal; and a detector circuit to compare the phase of the first clock signal with the phase of the input clock signal, to generate the information indicative of whether the phase of the first clock signal leads or lags the phase of the input clock signal.

Claim 60

Dependent Claim 20 words

The clock synchronization circuit of claim 52 wherein the plurality of delay stages is an even number of delay stages.

Claim 61

Dependent Claim 25 words

The clock synchronization circuit of claim 52 further comprising a buffer to output the reference clock signal, wherein the buffer receives the input clock signal.

Claim 62

Dependent Claim 91 words

The clock synchronization circuit of claim 52 wherein each delay stage of the plurality of delay stages comprises: a first output terminal; a second output terminal; a first transistor having a source, a drain, and a gate, the source and gate being coupled to the first output terminal, and the drain being coupled to the second output terminal; and a second transistor having a source, a drain, and a gate, the source and gate being coupled to the second output terminal, and the drain being coupled to the first output terminal.

Claim 63

Dependent Claim 21 words

The clock synchronization circuit of claim 52 wherein the plurality of delay stages is included in a phase locked loop circuit.

Claim 64

Dependent Claim 24 words

The clock synchronization circuit of claim 52 further comprising selection circuitry to select the pair of clock signals from the plurality of clock signals.

Claim 65

Dependent Claim 54 words

The clock synchronization circuit of claim 52 wherein the detector circuit comprises a phase detector to compare the phase of the first clock signal with the phase of the input clock signal, the phase detector to generate a binary signal that indicates whether the first clock signal leads or lags the input clock signal.

Claim 66

Dependent Claim 109 words

The clock synchronization circuit of claim 52 wherein the detector circuit comprises: a counter circuit to change a count value in a first direction when the phase of the input clock signal lags the phase of the first clock signal, and change the count value in a second direction when the phase of the input clock signal leads the phase of the first clock signal; and a digital to analog converter circuit to generate an analog control signal from the count value, wherein the analog control signal steers the phase of the first clock signal between the respective phases of each clock signal of the pair of clock signals.

Claim 67

Dependent Claim 159 words

A synchronous memory device comprising: an array of memory cells to store data; clock synchronization circuitry including: a plurality of delay stages coupled in series; a first multiplexer circuit, coupled to the plurality of delay stages, to perform selection of a delay time for a first internal clock signal, the selection being controlled by a first plurality of control signals; a first shift register circuit to generate the first plurality of control signals in accordance with information indicative of whether a phase of an external clock signal leads or lags a phase of an internal transmit clock signal; and a detector circuit to compare the phase of the external clock signal with the phase of the internal transmit clock signal and generate the information; and interface circuitry to output data from the memory device, the data being output in synchronism with the internal transmit clock signal, the internal transmit clock signal being generated using the first internal clock signal.

Claim 68

Dependent Claim 159 words

A synchronous memory device comprising: an array of memory cells to store data; clock synchronization circuitry including: a plurality of delay stages coupled in series; a first multiplexer circuit, coupled to the plurality of delay stages, to perform selection of a delay time for a first internal clock signal, the selection being controlled by a first plurality of control signals; a first shift register circuit to generate the first plurality of control signals in accordance with information indicative of whether a phase of an external clock signal leads or lags a phase of an internal transmit clock signal; and a detector circuit to compare the phase of the external clock signal with the phase of the internal transmit clock signal and generate the information; and interface circuitry to output data from the memory device, the data being output in synchronism with the internal transmit clock signal, the internal transmit clock signal being generated using the first internal clock signal.

Claim 69

Dependent Claim 83 words

The memory device of claim 60 further comprising: a second multiplexer circuit, coupled to the plurality of delay stages, to perform selection of a delay time for a second internal clock signal, the selection being controlled by a second plurality of control signals; and a second shift register circuit to generate the second plurality of control signals in accordance with the information indicative of whether the phase of the external clock signal leads or lags the phase of the internal transmit clock signal.

Claim 70

Dependent Claim 70 words

The memory device of claim 61 further comprising: interpolator circuitry to generate the internal transmit clock signal by interpolating between phases of the first and a second internal clock signals in accordance with a control voltage; and a control circuit to generate the control voltage according to the information indicative of whether the phase of the external clock signal leads or lags the phase of the internal transmit clock signal.

Claim 71

Dependent Claim 41 words

The memory device of claim 62 wherein the control circuit comprises: a counter circuit to generate a digital count value based on the information; and a digital to analog converter to generate the control voltage based on the digital count value.

Claim 72

Dependent Claim 28 words

The memory device of claim 60 , wherein the first internal clock signal is generated by an output of a delay stage of the plurality of delay stages.

Claim 73

Dependent Claim 20 words

The memory device of claim 60 wherein the plurality of delay stages is included in a phase locked loop circuit.

Claim 74

Dependent Claim 151 words

A synchronous memory device comprising: an array of memory cells to store data; a plurality of delay elements coupled in series, each delay element generating a respective output signal having a different phase; a detector circuit to compare a phase of an external clock signal with a phase of an internal transmit clock signal, the detector circuit to generate information indicative of whether the phase of the external clock signal leads or lags the phase of the internal transmit clock signal; a multiplexer circuit, coupled to the plurality of delay elements, to select a first output signal generated by the plurality of delay elements in response to the information; and an interface circuit to output data from the memory device, the data being output in synchronism with the internal transmit clock signal, the internal transmit clock signal being generated using at least the first output signal selected by the multiplexer circuit.

Claim 75

Dependent Claim 151 words

A synchronous memory device comprising: an array of memory cells to store data; a plurality of delay elements coupled in series, each delay element generating a respective output signal having a different phase; a detector circuit to compare a phase of an external clock signal with a phase of an internal transmit clock signal, the detector circuit to generate information indicative of whether the phase of the external clock signal leads or lags the phase of the internal transmit clock signal; a multiplexer circuit, coupled to the plurality of delay elements, to select a first output signal generated by the plurality of delay elements in response to the information; and an interface circuit to output data from the memory device, the data being output in synchronism with the internal transmit clock signal, the internal transmit clock signal being generated using at least the first output signal selected by the multiplexer circuit.

Claim 76

Dependent Claim 24 words

The memory device of claim 66 further comprising a shift register coupled to the multiplexer circuit to control selection of the first output signal.

Claim 77

Dependent Claim 75 words

The memory device of claim 66 further comprising: a control circuit to generate a control voltage that is responsive to the information; and interpolator circuitry to generate the internal transmit clock signal using the first output signal and a second output signal generated by the plurality of delay elements, the phase of the internal transmit clock signal being interpolated between the phases of the first and second output signals in response to the control voltage.

Claim 78

Dependent Claim 41 words

The memory device of claim 68 wherein the control circuit comprises: a digital converter to generate a digital count value in response to the information; and a digital to analog converter to generate the control voltage using the digital count value.

Claim 79

Dependent Claim 20 words

The memory device of claim 66 wherein the plurality of delay elements is included in a phase locked loop circuit.

Claim 80

Dependent Claim 121 words

A clock synchronization circuit comprising: a plurality of delay stages coupled in series to output a plurality of clock signals, each delay stage having a respective delay time with respect to a reference clock signal; and interpolator circuitry coupled to the plurality of delay stages, the interpolator circuitry to generate a first clock signal using a pair of clock signals of the plurality of clock signals, wherein a phase of the first clock signal is interpolated between respective phases of each clock signal of the pair of clock signals in accordance with information indicative of whether the phase of the first clock signal leads or lags a target phase, wherein the target phase is based on transitions in an input signal.

Claim 81

Dependent Claim 121 words

A clock synchronization circuit comprising: a plurality of delay stages coupled in series to output a plurality of clock signals, each delay stage having a respective delay time with respect to a reference clock signal; and interpolator circuitry coupled to the plurality of delay stages, the interpolator circuitry to generate a first clock signal using a pair of clock signals of the plurality of clock signals, wherein a phase of the first clock signal is interpolated between respective phases of each clock signal of the pair of clock signals in accordance with information indicative of whether the phase of the first clock signal leads or lags a target phase, wherein the target phase is based on transitions in an input signal.

Claim 82

Dependent Claim 55 words

The clock synchronization circuit of claim 71 further comprising detector circuitry coupled to the interpolator circuitry, the detector circuitry to compare the phase of the first clock signal with the target phase, the detector circuitry to generate the information indicative of whether the phase of the first clock signal leads or lags the target phase.

Claim 83

Dependent Claim 82 words

The clock synchronization circuit of claim 72 wherein the detector circuitry comprises a counter circuit to change a count value in a first direction when the target phase lags the phase of the first clock signal, and change the count value in a second direction when the target phase leads the phase of the first clock signal, wherein the information indicative of whether the phase of the first clock signal leads or lags the target phase is based on the count value.

Claim 84

Dependent Claim 97 words

The clock synchronization circuit of claim 73 wherein the information indicative of whether the phase of the first clock signal leads or lags the target phase is provided as an analog control signal, and wherein the detector circuitry further comprises a digital to analog converter circuit coupled to the counter circuit, the digital to analog converter circuit to generate the analog control signal from the count value, wherein the analog control signal controls interpolation between the respective phases of the clock signals of the pair of clock signals to produce the phase of the first clock signal.

Claim 85

Dependent Claim 20 words

The clock synchronization circuit of claim 71 wherein the target phase is detected based on sampling of the input signal.

Claim 86

Dependent Claim 18 words

The clock synchronization circuit of claim 75 wherein the input signal is sampled using the first clock signal.

Claim 87

Dependent Claim 15 words

The clock synchronization circuit of claim 76 wherein the input signal is a clock signal.

Claim 88

Dependent Claim 14 words

The clock synchronization circuit of claim 71 wherein the input signal includes clock information.

Claim 89

Dependent Claim 15 words

The clock synchronization circuit of claim 78 wherein the input signal is a clock signal.

Claim 90

Dependent Claim 24 words

The clock synchronization circuit of claim 79 wherein the input signal and the reference clock signal are both derived from an external clock signal.

Claim 91

Dependent Claim 16 words

The clock synchronization circuit of claim 80 wherein the input signal is the reference clock signal.

Claim 92

Dependent Claim 20 words

The clock synchronization circuit of claim 71 wherein the plurality of delay stages is an even number of delay stages.

Claim 93

Dependent Claim 25 words

The clock synchronization circuit of claim 71 wherein the plurality of delay stages and the interpolator circuitry are formed on a single integrated circuit device.

Claim 94

Dependent Claim 30 words

The clock synchronization circuit of claim 83 further comprising a buffer coupled to the interpolator circuitry, the buffer to receive the input signal from external to the integrated circuit device.

Claim 95

Dependent Claim 33 words

The clock synchronization circuit of claim 83 further comprising a buffer coupled to the plurality of delay stages, the buffer to receive the reference clock signal from external to the integrated circuit device.

Claim 96

Dependent Claim 91 words

The clock synchronization circuit of claim 71 wherein each delay stage of the plurality of delay stages comprises: a first output terminal; a second output terminal; a first transistor having a source, a drain, and a gate, the source and gate being coupled to the first output terminal, and the drain being coupled to the second output terminal; and a second transistor having a source, a drain, and a gate, the source and gate being coupled to the second output terminal, and the drain being coupled to the first output terminal.

Claim 97

Dependent Claim 21 words

The clock synchronization circuit of claim 71 wherein the plurality of delay stages is included in a phase locked loop circuit.

Claim 98

Dependent Claim 32 words

The clock synchronization circuit of claim 71 further comprising selection circuitry coupled to the interpolator circuitry, the selection circuitry to select the pair of clock signals from the plurality of clock signals.

Claim 99

Dependent Claim 55 words

The clock synchronization circuit of claim 71 further comprising a phase detector to compare the phase of the first clock signal with the target phase, and to generate the information indicative of whether the phase of the first clock signal leads or lags the target phase, wherein the information is represented by a binary signal.

Claim 100

Dependent Claim 35 words

The clock synchronization circuit of claim 71 wherein each delay stage of the plurality of delay stages generates complementary outputs, wherein each output of the complementary outputs is one of the plurality of clock signals.

Claim 101

Independent Claim 129 words

A method for clock synchronization, comprising: generating a plurality of clock signals from a reference clock signal, wherein each clock signal of the plurality of clock signals is delayed from the reference clock signal by a corresponding delay time such that a plurality of different delays with respect to the reference clock signal are represented in the plurality of clock signals; detecting phase of an input signal, wherein the phase of the input signal represents a target phase; and generating a first clock signal based on a pair of clock signals of the plurality of clock signals, wherein generating the first clock signal includes interpolation between the pair of clock signals using information indicative of whether the phase of the first clock signal leads or lags the target phase.

Claim 102

Independent Claim 129 words

A method for clock synchronization, comprising: generating a plurality of clock signals from a reference clock signal, wherein each clock signal of the plurality of clock signals is delayed from the reference clock signal by a corresponding delay time such that a plurality of different delays with respect to the reference clock signal are represented in the plurality of clock signals; detecting phase of an input signal, wherein the phase of the input signal represents a target phase; and generating a first clock signal based on a pair of clock signals of the plurality of clock signals, wherein generating the first clock signal includes interpolation between the pair of clock signals using information indicative of whether the phase of the first clock signal leads or lags the target phase.

Claim 103

Dependent Claim 18 words

The method of claim 91 wherein detecting phase of the input signal further comprises sampling the input signal.

Claim 104

Dependent Claim 22 words

The method of claim 92 wherein sampling the input signal further comprises sampling the input signal based on the first clock signal.

Claim 105

Dependent Claim 13 words

The method of claim 93 wherein the input signal is a clock signal.

Claim 106

Dependent Claim 21 words

The method of claim 94 wherein the input signal and the reference clock signal are generated from an external clock signal.

Claim 107

Dependent Claim 27 words

The method of claim 92 further comprises selecting the pair of clock signals from the plurality of clock signals based on the sampling of the input signal.

Claim 108

Dependent Claim 57 words

The method of claim 91 wherein generating the plurality of clock signals further comprises generating the plurality of clock signals using a plurality of delay stages coupled in series, wherein each delay stage of the plurality of delay stages generates complementary outputs, wherein each output of the complementary outputs is one of the plurality of clock signals.

Claim 109

Dependent Claim 12 words

The method of claim 91 wherein the input signal includes clock information.

Claim 110

Dependent Claim 13 words

The method of claim 98 wherein the input signal is a clock signal.

Claim 111

Dependent Claim 176 words

An integrated circuit comprising: a plurality of delay stages coupled in series to output a plurality of clock signals, each delay stage of the plurality of delay stages having a delay time with respect to a reference clock signal; a phase detector to determine the phase of an input signal by sampling the input signal, wherein the phase of the input signal is based on at least one transition in the input signal, the phase detector to generate information indicative of whether a phase of a first clock signal leads or lags the phase of the input signal; and interpolator circuitry coupled to the plurality of delay stages and the phase detector, the interpolator circuitry to generate the first clock signal using a pair of clock signals of the plurality of clock signals, wherein the phase of the first clock signal is interpolated between respective phases of the pair of clock signals in accordance with the information indicative of whether the phase of the first clock signal leads or lags the phase of the input signal.

Claim 112

Dependent Claim 176 words

An integrated circuit comprising: a plurality of delay stages coupled in series to output a plurality of clock signals, each delay stage of the plurality of delay stages having a delay time with respect to a reference clock signal; a phase detector to determine the phase of an input signal by sampling the input signal, wherein the phase of the input signal is based on at least one transition in the input signal, the phase detector to generate information indicative of whether a phase of a first clock signal leads or lags the phase of the input signal; and interpolator circuitry coupled to the plurality of delay stages and the phase detector, the interpolator circuitry to generate the first clock signal using a pair of clock signals of the plurality of clock signals, wherein the phase of the first clock signal is interpolated between respective phases of the pair of clock signals in accordance with the information indicative of whether the phase of the first clock signal leads or lags the phase of the input signal.

Claim 113

Dependent Claim 19 words

The integrated circuit of claim 100 wherein the phase detector samples the input signal using the first clock signal.

Claim 114

Dependent Claim 13 words

The integrated circuit of claim 100 wherein the input signal includes clock information.

Claim 115

Dependent Claim 14 words

The integrated circuit of claim 102 wherein the input signal is a clock signal.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2007-03-30	2007-09-29	2008-03-30	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2011-03-30	2011-09-29	2012-03-30	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2015-03-30	2015-09-29	2016-03-30	$7700.00	Window Closed / Lapsed

Delay stage circuitry for a ring oscillator

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