US5140688A — GaAs integrated circuit programmable delay line e…

Claim 1

Independent Claim 176 words

A semiconductor chip for processing or storing information comprising: (a) clock input circuitry connected to a first chip for receiving clock signals of a first frequency therefrom; (b) clock output circuitry connected to a second chip for transmitting said clock signals to said second chip; (c) transmission/receiving circuitry connected to said first chip for receiving data therefrom and connected to said second chip for transmitting data thereto, said transmission/receiving circuitry including means to sample said data at a second frequency less than said first frequency; and (d) circuit components operatively coupled to said clock input circuitry and transmission/receiving circuitry for processing said data, (e) said circuit components include a memory array for storing data receivable via said transmission/receiving circuitry in a digital form and for providing storable data to said transmission circuitry; and (f) said transmission circuitry includes a first transmission path for transmitting data received from said first chip directly to said second chip and means including a second transmission path for combining data which is stored in said memory array with other stored data.

Claim 2

Dependent Claim 176 words

A semiconductor chip for processing or storing information comprising: (a) clock input circuitry connected to a first chip for receiving clock signals of a first frequency therefrom; (b) clock output circuitry connected to a second chip for transmitting said clock signals to said second chip; (c) transmission/receiving circuitry connected to said first chip for receiving data therefrom and connected to said second chip for transmitting data thereto, said transmission/receiving circuitry including means to sample said data at a second frequency less than said first frequency; and (d) circuit components operatively coupled to said clock input circuitry and transmission/receiving circuitry for processing said data, (e) said circuit components include a memory array for storing data receivable via said transmission/receiving circuitry in a digital form and for providing storable data to said transmission circuitry; and (f) said transmission circuitry includes a first transmission path for transmitting data received from said first chip directly to said second chip and means including a second transmission path for combining data which is stored in said memory array with other stored data.

Claim 3

Dependent Claim 153 words

A semiconductor chip for processing or storing information comprising: (a) clock input circuitry connected to a first chip for receiving clock signals of a first frequency therefrom, said clock input circuitry includes plural signal paths for receiving multiple clock signals; (b) clock output circuitry connected to a second chip for transmitting said clock signals to said second chip, said clock output circuitry includes plural paths for outputting said multiple clock signals; (c) transmission/receiving circuitry connected to said first chip for receiving data therefrom and connected to said second chip for transmitting data thereto, said transmission/receiving circuitry including means to sample said data at a second frequency less than said first frequency; and (d) circuit components operatively coupled to said clock input circuitry, said circuit components receiving first and second clock frequencies, the first clock frequency being a multiple of the frequency of the second clock frequency and transmission/receiving circuitry for processing said data.

Claim 4

Dependent Claim 153 words

A semiconductor chip for processing or storing information comprising: (a) clock input circuitry connected to a first chip for receiving clock signals of a first frequency therefrom, said clock input circuitry includes plural signal paths for receiving multiple clock signals; (b) clock output circuitry connected to a second chip for transmitting said clock signals to said second chip, said clock output circuitry includes plural paths for outputting said multiple clock signals; (c) transmission/receiving circuitry connected to said first chip for receiving data therefrom and connected to said second chip for transmitting data thereto, said transmission/receiving circuitry including means to sample said data at a second frequency less than said first frequency; and (d) circuit components operatively coupled to said clock input circuitry, said circuit components receiving first and second clock frequencies, the first clock frequency being a multiple of the frequency of the second clock frequency and transmission/receiving circuitry for processing said data.

Claim 5

Independent Claim 246 words

A system for processing or storing digitized information comprising: (a) a plurality of synchronous semiconductor chips electrically connected in a cascade arrangement to effect serial flow of timing signals and data through said plurality of chips, each chip including: (b) clock input circuitry for receiving timing signals at a first frequency from a preceding chip in said cascade arrangement; (c) clock output circuitry for serially transmitting received clock signals to a subsequent chip in said cascade arrangement; (d) data transmission circuitry serially connected to a preceding chip for receiving digital data therefrom and serially connected to a subsequent chip for transmitting data thereto, said transmission circuitry includes a first transmission path for providing data received from a preceding chip to a subsequent chip and a second transmission path for serially providing data stored in said memory array to a subsequent chip; (e) circuit components operatively coupled to said clock circuitry and transmission circuitry for processing said digital data, said circuit components include a memory array and an address generator for storing and reading out data with a programmable delay via said transmission circuitry; (f) second input circuitry for selecting a variable delay between the time data that is received onto the chip and the time data that is transmitted from the chip, and (g) further including plural said second transmission paths, wherein said second transmission paths of adjoining chips in said cascade arrangement are serially connected with one another to assimilate data stored on different chips.

Claim 6

Independent Claim 246 words

A system for processing or storing digitized information comprising: (a) a plurality of synchronous semiconductor chips electrically connected in a cascade arrangement to effect serial flow of timing signals and data through said plurality of chips, each chip including: (b) clock input circuitry for receiving timing signals at a first frequency from a preceding chip in said cascade arrangement; (c) clock output circuitry for serially transmitting received clock signals to a subsequent chip in said cascade arrangement; (d) data transmission circuitry serially connected to a preceding chip for receiving digital data therefrom and serially connected to a subsequent chip for transmitting data thereto, said transmission circuitry includes a first transmission path for providing data received from a preceding chip to a subsequent chip and a second transmission path for serially providing data stored in said memory array to a subsequent chip; (e) circuit components operatively coupled to said clock circuitry and transmission circuitry for processing said digital data, said circuit components include a memory array and an address generator for storing and reading out data with a programmable delay via said transmission circuitry; (f) second input circuitry for selecting a variable delay between the time data that is received onto the chip and the time data that is transmitted from the chip, and (g) further including plural said second transmission paths, wherein said second transmission paths of adjoining chips in said cascade arrangement are serially connected with one another to assimilate data stored on different chips.

Claim 7

Independent Claim 230 words

A system for processing or storing digitized information wherein said system is configured as a digital rf memory system for storing and transmitting rf data with a programmable delay comprising: (a) a first converter for digitizing analog rf data; (b) a second converter for restoring digitized rf data to analog form, (c) a plurality of synchronous semiconductor chips electrically connected in a cascade arrangement to effect serial flow of timing signals and data through said plurality of chips, said cascade arrangement including N chips, a first chip in said cascade arrangement receiving digitized data from said first converter and the last chip in said cascade arrangement coupled to provide digitized data to said second converter, each said chip including: (d) clock input circuitry for receiving timing signals at a first frequency from a preceding chip in said cascade arrangement; (e) clock output circuitry for serially transmitting received clock signals to a subsequent chip in said cascade arrangement; (f) data transmission circuitry serially connected to a preceding chip for receiving digital data therefrom and serially connected to a subsequent chip for transmitting data thereto; (g) circuit components operatively coupled to said clock circuitry and transmission circuitry for processing said digital data; and (h) second input circuitry for selecting a variable delay between the time data that is received onto the chip and the time data that is transmitted from the chip.

Claim 8

Independent Claim 230 words

A system for processing or storing digitized information wherein said system is configured as a digital rf memory system for storing and transmitting rf data with a programmable delay comprising: (a) a first converter for digitizing analog rf data; (b) a second converter for restoring digitized rf data to analog form, (c) a plurality of synchronous semiconductor chips electrically connected in a cascade arrangement to effect serial flow of timing signals and data through said plurality of chips, said cascade arrangement including N chips, a first chip in said cascade arrangement receiving digitized data from said first converter and the last chip in said cascade arrangement coupled to provide digitized data to said second converter, each said chip including: (d) clock input circuitry for receiving timing signals at a first frequency from a preceding chip in said cascade arrangement; (e) clock output circuitry for serially transmitting received clock signals to a subsequent chip in said cascade arrangement; (f) data transmission circuitry serially connected to a preceding chip for receiving digital data therefrom and serially connected to a subsequent chip for transmitting data thereto; (g) circuit components operatively coupled to said clock circuitry and transmission circuitry for processing said digital data; and (h) second input circuitry for selecting a variable delay between the time data that is received onto the chip and the time data that is transmitted from the chip.

Claim 9

Dependent Claim 76 words

The system of claim 4 wherein the first converter transforms analog data into multibit digital words and outputs each word as parallel bit streams, said system further comprising: a plurality of additional cascaded arrangements of synchronous chips, each arrangement including N chips, the first chip in each arrangement coupled to receive a bit stream of data from the first converter and the last chip in the arrangement coupled to provide digitized data to the second converter.

Claim 10

Dependent Claim 13 words

The system of claim 5 wherein the first converter generates four bit streams.

Claim 11

Dependent Claim 192 words

A semiconductor chip for processing or storing information comprising; (a) clock input circuitry connected to a first chip for receiving clock signals at a first frequency; (b) clock output circuitry connected to a second chip for transmitting said clock signals to the second chip; (c) transmission circuitry connected to said first chip for receiving data therefrom and connected to said second chip for transmitting data thereto; (d) circuit components operatively coupled to said clock input and clock output circuitry and said transmission circuitry for processing said data; and (e) circuitry for selecting a variable delay between the time data is received onto the chip and transmitted from the chip, and (f) wherein the circuit components include a random access memory for storage of digital data, said transmission circuitry capable of sampling the data at a second frequency less than the first frequency, said components capable of writing a datum of information to a write address in said memory and reading another datum of information from a read address in said memory within a cycle of the second frequency, and said variable delay being proportional to differences between the read and write addresses.

Claim 12

Dependent Claim 192 words

A semiconductor chip for processing or storing information comprising; (a) clock input circuitry connected to a first chip for receiving clock signals at a first frequency; (b) clock output circuitry connected to a second chip for transmitting said clock signals to the second chip; (c) transmission circuitry connected to said first chip for receiving data therefrom and connected to said second chip for transmitting data thereto; (d) circuit components operatively coupled to said clock input and clock output circuitry and said transmission circuitry for processing said data; and (e) circuitry for selecting a variable delay between the time data is received onto the chip and transmitted from the chip, and (f) wherein the circuit components include a random access memory for storage of digital data, said transmission circuitry capable of sampling the data at a second frequency less than the first frequency, said components capable of writing a datum of information to a write address in said memory and reading another datum of information from a read address in said memory within a cycle of the second frequency, and said variable delay being proportional to differences between the read and write addresses.

Claim 13

Dependent Claim 26 words

The semiconductor chip of claim 7 wherein said transmission circuitry samples and stores data at a second clock frequency which is less than said first frequency.

Claim 14

Independent Claim 223 words

A system for processing or storing digitized information comprising: a plurality of synchronous semiconductor chips electrically connected in a cascade arrangement to effect serial flow of timing signals and data through the plurality of chips, each chip includes a memory array for storing data receivable via transmission circuitry and for providing storable data to the transmission circuitry, and each chip including: clock input circuitry for receiving timing signals of a first frequency from any serially connected preceding chips in the cascade arrangement; clock output circuitry for serially transmitting received clock signals to any subsequent chips in the cascade arrangement; data transmission circuitry serially connected to any preceding chips for receiving digital data therefrom and serially connected to any subsequent chips for transmitting data thereto, said transmission circuitry capable of sampling the data at a second clock frequency less than the first frequency, and the transmission circuitry includes a first transmission path for receiving data from any preceding chip in the cascade arrangement and providing the data to any subsequent chip in the cascade arrangement, the transmission circuitry further including a second transmission path capable of combining data which is stored in the memory array with data which is stored in other chips in the cascade arrangement; and circuit components operatively coupled to the clock circuitry and transmission circuitry for processing the digital data.

Claim 15

Independent Claim 223 words

A system for processing or storing digitized information comprising: a plurality of synchronous semiconductor chips electrically connected in a cascade arrangement to effect serial flow of timing signals and data through the plurality of chips, each chip includes a memory array for storing data receivable via transmission circuitry and for providing storable data to the transmission circuitry, and each chip including: clock input circuitry for receiving timing signals of a first frequency from any serially connected preceding chips in the cascade arrangement; clock output circuitry for serially transmitting received clock signals to any subsequent chips in the cascade arrangement; data transmission circuitry serially connected to any preceding chips for receiving digital data therefrom and serially connected to any subsequent chips for transmitting data thereto, said transmission circuitry capable of sampling the data at a second clock frequency less than the first frequency, and the transmission circuitry includes a first transmission path for receiving data from any preceding chip in the cascade arrangement and providing the data to any subsequent chip in the cascade arrangement, the transmission circuitry further including a second transmission path capable of combining data which is stored in the memory array with data which is stored in other chips in the cascade arrangement; and circuit components operatively coupled to the clock circuitry and transmission circuitry for processing the digital data.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1995-08-18	1996-02-17	1996-08-18	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1999-08-18	2000-02-17	2000-08-18	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2003-08-18	2004-02-17	2004-08-18	$7700.00	Window Closed / Lapsed

GaAs integrated circuit programmable delay line element

Abstract

Inventors

Bibliographic Details

Claims Analysis

References Cited (Backward Citations)

USPTO Annuity & Maintenance Windows

Assigned Categories & Tags

Assign Category Tag