Methods of fabricating a dielectric plug in MOSFETS to suppress short-channel effects

Claim 1

A method of fabricating a short-channel Metal-Oxide-Silicon Field Effect Transistor (MOSFET) device including a gate electrode stack and doped source and drain regions disposed on each side of a channel region located under the gate electrode stack over a substrate, comprising: etching the doped source and drain regions to create recessed regions in the substrate adjacent to, and recessed with respect to the gate electrode stack and the channel region, and to expose sidewalls in the doped source and drain regions; forming an oxide layer over the exposed sidewalls in the doped source and drain regions and over the recessed regions in the substrate; and removing the formed oxide layer to expose the substrate in the recessed regions of the source and drain regions and to leave a portion of the formed oxide layer on the exposed sidewalls of the source and drain to form a dielectric spacer and to surround a channel region between the source and drain regions.

Claim 2

A method of fabricating a short-channel Metal-Oxide-Silicon Field Effect Transistor (MOSFET) device including a gate electrode stack and doped source and drain regions disposed on each side of a channel region located under the gate electrode stack over a substrate, comprising: etching the doped source and drain regions to create recessed regions in the substrate adjacent to, and recessed with respect to the gate electrode stack and the channel region, and to expose sidewalls in the doped source and drain regions; forming an oxide layer over the exposed sidewalls in the doped source and drain regions and over the recessed regions in the substrate; and removing the formed oxide layer to expose the substrate in the recessed regions of the source and drain regions and to leave a portion of the formed oxide layer on the exposed sidewalls of the source and drain to form a dielectric spacer and to surround a channel region between the source and drain regions.

Claim 3

A method of fabricating a short channel Metal-Oxide-Silicon Field Effect Transistor (MOSFET) device including a gate electrode stack and source and drain regions disposed adjacent to the gate electrode stack over a substrate, comprising: forming an oxide layer over exposed source and drain regions in the substrate, wherein forming the oxide layer comprises; providing the substrate including an active region surrounded by an isolation region, a gate electrode stack disposed over the active region, a protective cap layer disposed over the gate electrode stack, a pair of low doping drain (LDD) regions disposed in the substrate such that the formed LDD regions are disposed adjacent to the gate electrode stack and are disposed apart from each other at opposite sides of the gate electrode stack, and a first spacer layer disposed around the gate electrode stack such that the disposed first spacer layer together with the disposed protective cap layer encloses the gate electrode stack; removing a first layer in the substrate by etching the substrate to expose a sidewall in the LDD regions recessed with respect to the first spacer layer to further expose the substrate around the gate electrode stack to form source and drain regions adjacent to the exposed LDD regions; forming a second spacer layer over the first spacer layer such that the formed second spacer layer extends from the exposed source and drain regions; removing a second layer in the substrate around the formed second spacer layer and the source and drain regions to further expose the substrate around the LDD regions such that the exposed substrate extends the formed sidewall in the LDD regions further into the substrate to form recesses in the source and drain regions: forming the an oxide layer over the exposed substrate in the formed source and drain recesses such that the formed second spacer layer together with the formed oxide layer closes the exposed LDD regions; and further comprising, removing the formed oxide layer to expose the substrate in the recesses and to leave a portion of the formed oxide layer in the recesses to form a dielectric spacer to surround a channel region between the source and drain regions.

Claim 4

A method of fabricating a short channel Metal-Oxide-Silicon Field Effect Transistor (MOSFET) device including a gate electrode stack and source and drain regions disposed adjacent to the gate electrode stack over a substrate, comprising: forming an oxide layer over exposed source and drain regions in the substrate, wherein forming the oxide layer comprises; providing the substrate including an active region surrounded by an isolation region, a gate electrode stack disposed over the active region, a protective cap layer disposed over the gate electrode stack, a pair of low doping drain (LDD) regions disposed in the substrate such that the formed LDD regions are disposed adjacent to the gate electrode stack and are disposed apart from each other at opposite sides of the gate electrode stack, and a first spacer layer disposed around the gate electrode stack such that the disposed first spacer layer together with the disposed protective cap layer encloses the gate electrode stack; removing a first layer in the substrate by etching the substrate to expose a sidewall in the LDD regions recessed with respect to the first spacer layer to further expose the substrate around the gate electrode stack to form source and drain regions adjacent to the exposed LDD regions; forming a second spacer layer over the first spacer layer such that the formed second spacer layer extends from the exposed source and drain regions; removing a second layer in the substrate around the formed second spacer layer and the source and drain regions to further expose the substrate around the LDD regions such that the exposed substrate extends the formed sidewall in the LDD regions further into the substrate to form recesses in the source and drain regions: forming the an oxide layer over the exposed substrate in the formed source and drain recesses such that the formed second spacer layer together with the formed oxide layer closes the exposed LDD regions; and further comprising, removing the formed oxide layer to expose the substrate in the recesses and to leave a portion of the formed oxide layer in the recesses to form a dielectric spacer to surround a channel region between the source and drain regions.

Claim 7

A method of fabricating a semiconductor device, comprising: providing a substrate including an active region surrounded by an isolation region, and a gate electrode stack disposed over the active region; forming a protective cap layer over the gate electrode stack; forming a pair of low doping drain (LDD) regions by implanting a dopant into the substrate such that the formed LDD regions are disposed adjacent to the gate electrode stack and are disposed apart from each other at opposite sides of the gate electrode stack; forming a first spacer layer around the gate electrode stack and such that the formed first spacer layer together with the formed protective cap layer covers the gate electrode stack; removing a first layer in the substrate by etching the substrate to expose a sidewall in the LDD regions and under the first spacer layer to further expose the substrate around the gate electrode stack to form source and drain regions adjacent to the exposed LDD regions; forming a second spacer layer over the first spacer layer such that the formed second spacer layer extends from the exposed source and drain regions; removing a second layer in the substrate around the formed second spacer layer and the source and drain regions to further expose the substrate around the LDD regions such that the exposed substrate extends the formed sidewall in the LDD regions further into the substrate to form recesses in the source and drain regions; forming an oxide layer over the exposed substrate in the formed source and drain recesses such that the formed second spacer layer together with the formed oxide layer closes the exposed LDD regions; removing the second spacer layer by selective etching to expose the closed LDD regions; removing the formed oxide layer from the source and drain regions by oxide spacer etching to expose the substrate in the source and drain regions and to leave a portion of the oxide layer in the recesses to form a dielectric plug in each of the recess and surround a channel region below the gate electrode stack and between the source and drain regions; and depositing epitaxial silicon on the exposed substrate such that the deposited epitaxial silicon fills the formed recesses in the source and drain regions to create a connection between the channel and the filled source and drain regions.

Claim 8

A method of fabricating a semiconductor device, comprising: providing a substrate including an active region surrounded by an isolation region, and a gate electrode stack disposed over the active region; forming a protective cap layer over the gate electrode stack; forming a pair of low doping drain (LDD) regions by implanting a dopant into the substrate such that the formed LDD regions are disposed adjacent to the gate electrode stack and are disposed apart from each other at opposite sides of the gate electrode stack; forming a first spacer layer around the gate electrode stack and such that the formed first spacer layer together with the formed protective cap layer covers the gate electrode stack; removing a first layer in the substrate by etching the substrate to expose a sidewall in the LDD regions and under the first spacer layer to further expose the substrate around the gate electrode stack to form source and drain regions adjacent to the exposed LDD regions; forming a second spacer layer over the first spacer layer such that the formed second spacer layer extends from the exposed source and drain regions; removing a second layer in the substrate around the formed second spacer layer and the source and drain regions to further expose the substrate around the LDD regions such that the exposed substrate extends the formed sidewall in the LDD regions further into the substrate to form recesses in the source and drain regions; forming an oxide layer over the exposed substrate in the formed source and drain recesses such that the formed second spacer layer together with the formed oxide layer closes the exposed LDD regions; removing the second spacer layer by selective etching to expose the closed LDD regions; removing the formed oxide layer from the source and drain regions by oxide spacer etching to expose the substrate in the source and drain regions and to leave a portion of the oxide layer in the recesses to form a dielectric plug in each of the recess and surround a channel region below the gate electrode stack and between the source and drain regions; and depositing epitaxial silicon on the exposed substrate such that the deposited epitaxial silicon fills the formed recesses in the source and drain regions to create a connection between the channel and the filled source and drain regions.

Claim 12

A method of fabricating a short-channel Metal-Oxide-Silicon Field Effect Transistor (MOSFET) device on a substrate including an active region surrounded by an isolation region, a gate electrode stack disposed over the active region, a dielectric protective cap layer disposed over the gate electrode stack, a pair of low doping drain (LDD) regions disposed in the substrate such that the formed LDD regions are disposed adjacent to the gate electrode stack and are disposed apart from each other at opposite sides of the gate electrode stack, and a first spacer layer disposed around the gate electrode stack such that the disposed first spacer layer together with the disposed protective cap layer covers the gate electrode stack, comprising: removing a first layer in the substrate in the range of about 50Å to 700Å by etching the substrate to expose a sidewall in the LDD regions and under the first spacer layer, to further expose the substrate around the gate electrode stack to form source and drain regions adjacent to the exposed LDD regions; forming a second spacer layer over the rest spacer layer such that the formed second spacer layer extends from the exposed source and drain regions; etching to remove a second layer in the substrate around the formed second spacer layer and the source and drain regions to further expose the substrate around the LDD regions such that the exposed substrate extends the formed sidewall in the LDD regions further into the substrate to form recesses in the source and drain regions, wherein the etching depth of the second layer in the substrate is greater than the source and drain regions; forming an oxide layer over the exposed substrate in the formed source and drain recesses such that the formed second spacer layer together with the formed oxide layer closes the exposed LDD regions; removing the second spacer layer by selective etching to expose the closed LDD regions; removing the formed oxide layer from the source and drain regions by oxide spacer etching to expose the substrate in the source and drain regions and to leave a portion of the oxide layer in the recesses to form a dielectric plug in each of the recess and surround a channel region between the source and drain regions; and depositing epitaxial silicon in the source and drain recesses such that the deposited epitaxial silicon fills the recesses to form the source and drain regions, and to connect the channel and the source and drain regions.

Claim 13

A method of fabricating a short-channel Metal-Oxide-Silicon Field Effect Transistor (MOSFET) device on a substrate including an active region surrounded by an isolation region, a gate electrode stack disposed over the active region, a dielectric protective cap layer disposed over the gate electrode stack, a pair of low doping drain (LDD) regions disposed in the substrate such that the formed LDD regions are disposed adjacent to the gate electrode stack and are disposed apart from each other at opposite sides of the gate electrode stack, and a first spacer layer disposed around the gate electrode stack such that the disposed first spacer layer together with the disposed protective cap layer covers the gate electrode stack, comprising: removing a first layer in the substrate in the range of about 50Å to 700Å by etching the substrate to expose a sidewall in the LDD regions and under the first spacer layer, to further expose the substrate around the gate electrode stack to form source and drain regions adjacent to the exposed LDD regions; forming a second spacer layer over the rest spacer layer such that the formed second spacer layer extends from the exposed source and drain regions; etching to remove a second layer in the substrate around the formed second spacer layer and the source and drain regions to further expose the substrate around the LDD regions such that the exposed substrate extends the formed sidewall in the LDD regions further into the substrate to form recesses in the source and drain regions, wherein the etching depth of the second layer in the substrate is greater than the source and drain regions; forming an oxide layer over the exposed substrate in the formed source and drain recesses such that the formed second spacer layer together with the formed oxide layer closes the exposed LDD regions; removing the second spacer layer by selective etching to expose the closed LDD regions; removing the formed oxide layer from the source and drain regions by oxide spacer etching to expose the substrate in the source and drain regions and to leave a portion of the oxide layer in the recesses to form a dielectric plug in each of the recess and surround a channel region between the source and drain regions; and depositing epitaxial silicon in the source and drain recesses such that the deposited epitaxial silicon fills the recesses to form the source and drain regions, and to connect the channel and the source and drain regions.

Claim 16

A method of fabricating a short-channel Metal-Oxide-Silicon Field Effect Transistor (MOSFET) device on a substrate including an active region surrounded by an isolation region, a gate electrode stack disposed over the active region, a dielectric protective cap layer disposed over the gate electrode stack, a pair of low doping drain (LDD) regions disposed in the substrate such that the formed LDD regions are disposed adjacent to the gate electrode stack and are disposed apart from each other at opposite sides of the gate electrode stack, and a first spacer layer disposed around the gate electrode stack such that the disposed first spacer layer together with the disposed protective cap layer covers the gate electrode stack, comprising: removing a first layer in the substrate in the range of about 50 Å to 700 Å by etching the substrate to expose a sidewall in the LDD regions and under the first spacer layer, to further expose the substrate around the gate electrode stack to form source and drain regions adjacent to the exposed LDD regions; forming a second silicon nitride spacer layer over the first spacer layer such that the formed second spacer layer extends from the exposed source and drain regions; etching to remove a second layer in the substrate around the formed second spacer layer and the source and drain regions to further expose the substrate around the LDD regions such that the exposed substrate extends the formed sidewall in the LDD regions further into the substrate to form recesses in the source and drain regions, wherein the etching depth of the second layer in the substrate is greater than the source and drain regions, wherein the etching depth of the second layer in the substrate is in the range of about 300 Å to 2000 Å; forming an oxide layer over the exposed substrate in the formed source and drain recesses such that the formed second spacer layer together with the formed oxide layer closes the exposed LDD regions; removing the second spacer layer by selective etching to expose the closed LDD regions; removing the formed oxide layer from the source and drain regions by oxide spacer etching to expose the substrate in the source and drain regions and to leave a portion of the oxide layer in the recesses to form a dielectric plug in each of the recess and surround a channel region between the source and drain regions; and depositing epitaxial silicon in the source and drain recesses such that the deposited epitaxial silicon fills the recesses to form the source and drain, regions, and to connect the channel and the source and drain regions.

Claim 17

A method of fabricating a short-channel Metal-Oxide-Silicon Field Effect Transistor (MOSFET) device on a substrate including an active region surrounded by an isolation region, a gate electrode stack disposed over the active region, a dielectric protective cap layer disposed over the gate electrode stack, a pair of low doping drain (LDD) regions disposed in the substrate such that the formed LDD regions are disposed adjacent to the gate electrode stack and are disposed apart from each other at opposite sides of the gate electrode stack, and a first spacer layer disposed around the gate electrode stack such that the disposed first spacer layer together with the disposed protective cap layer covers the gate electrode stack, comprising: removing a first layer in the substrate in the range of about 50 Å to 700 Å by etching the substrate to expose a sidewall in the LDD regions and under the first spacer layer, to further expose the substrate around the gate electrode stack to form source and drain regions adjacent to the exposed LDD regions; forming a second silicon nitride spacer layer over the first spacer layer such that the formed second spacer layer extends from the exposed source and drain regions; etching to remove a second layer in the substrate around the formed second spacer layer and the source and drain regions to further expose the substrate around the LDD regions such that the exposed substrate extends the formed sidewall in the LDD regions further into the substrate to form recesses in the source and drain regions, wherein the etching depth of the second layer in the substrate is greater than the source and drain regions, wherein the etching depth of the second layer in the substrate is in the range of about 300 Å to 2000 Å; forming an oxide layer over the exposed substrate in the formed source and drain recesses such that the formed second spacer layer together with the formed oxide layer closes the exposed LDD regions; removing the second spacer layer by selective etching to expose the closed LDD regions; removing the formed oxide layer from the source and drain regions by oxide spacer etching to expose the substrate in the source and drain regions and to leave a portion of the oxide layer in the recesses to form a dielectric plug in each of the recess and surround a channel region between the source and drain regions; and depositing epitaxial silicon in the source and drain recesses such that the deposited epitaxial silicon fills the recesses to form the source and drain, regions, and to connect the channel and the source and drain regions.

Claim 20

A method of fabricating a short-channel Metal-Oxide-Silicon Field Effect Transistor (MOSFET) device, comprising: providing a substrate including an active region surrounded by an isolation region, a gate electrode stack disposed over the active region, a protective cap layer disposed over the gate electrode stack, a pair of low doping drain (LDD) regions disposed in the substrate such that the formed LDD regions are disposed adjacent to the gate electrode stack and are disposed apart from each other at opposite sides of the gate electrode stack, and a first spacer layer disposed around the gate electrode stack such that the disposed first spacer layer together with the disposed protective cap layer encloses the game electrode stack; removing a first layer by etching the substrate in the range of about 50 Å to 700 Å to expose a sidewall in the LDD regions and under the first spacer layer, to further expose the substrate around the gate electrode stack to form source and drain regions adjacent to the exposed LDD regions; forming a second spacer layer over the first spacer layer in the range of about 300 Å to 2000 Å such that the formed second spacer layer extends from the exposed source and drain regions; removing a second layer in the substrate around the formed second spacer layer and the source and drain regions, to further expose the substrate around the LDD regions such that the exposed substrate extends the formed sidewall in the LDD regions further into the substrate to form recesses in the source and drain regions; forming an oxide layer over the exposed substrate in the formed source and drain recesses such that the formed second spacer layer together with the formed oxide layer closes the exposed LDD regions; removing the second spacer layer by selective etching to expose the closed LDD regions; removing the formed oxide layer from the source and drain recesses by oxide spacer etching to expose the substrate in the source and drain regions, to leave a portion of the oxide layer in the source and drain recesses to form a dielectric spacer in each of the recess and surround a channel region between the source and drain regions; pre-cleaning the sidewalls using HF dip prior to epitaxial silicon deposition to remove any oxide layer formed over and around the sidewalls of the LDD regions; depositing epitaxial silicon on the exposed substrate such that the deposited epitaxial silicon fills the formed recesses in the source and drain regions to connect the channel and the filled source and drain regions; and implanting P and N type dopants in the source and drain regions.

Claim 21

A method of fabricating a short-channel Metal-Oxide-Silicon Field Effect Transistor (MOSFET) device, comprising: providing a substrate including an active region surrounded by an isolation region, a gate electrode stack disposed over the active region, a protective cap layer disposed over the gate electrode stack, a pair of low doping drain (LDD) regions disposed in the substrate such that the formed LDD regions are disposed adjacent to the gate electrode stack and are disposed apart from each other at opposite sides of the gate electrode stack, and a first spacer layer disposed around the gate electrode stack such that the disposed first spacer layer together with the disposed protective cap layer encloses the game electrode stack; removing a first layer by etching the substrate in the range of about 50 Å to 700 Å to expose a sidewall in the LDD regions and under the first spacer layer, to further expose the substrate around the gate electrode stack to form source and drain regions adjacent to the exposed LDD regions; forming a second spacer layer over the first spacer layer in the range of about 300 Å to 2000 Å such that the formed second spacer layer extends from the exposed source and drain regions; removing a second layer in the substrate around the formed second spacer layer and the source and drain regions, to further expose the substrate around the LDD regions such that the exposed substrate extends the formed sidewall in the LDD regions further into the substrate to form recesses in the source and drain regions; forming an oxide layer over the exposed substrate in the formed source and drain recesses such that the formed second spacer layer together with the formed oxide layer closes the exposed LDD regions; removing the second spacer layer by selective etching to expose the closed LDD regions; removing the formed oxide layer from the source and drain recesses by oxide spacer etching to expose the substrate in the source and drain regions, to leave a portion of the oxide layer in the source and drain recesses to form a dielectric spacer in each of the recess and surround a channel region between the source and drain regions; pre-cleaning the sidewalls using HF dip prior to epitaxial silicon deposition to remove any oxide layer formed over and around the sidewalls of the LDD regions; depositing epitaxial silicon on the exposed substrate such that the deposited epitaxial silicon fills the formed recesses in the source and drain regions to connect the channel and the filled source and drain regions; and implanting P and N type dopants in the source and drain regions.

Claim 24

A method of fabricating a short-channel Metal-Oxide-Silicon Field Effect Transistor (MOSFET) device on a substrate including an active region surrounded by an isolation region, a gate electrode stack disposed over the active region, a protective cap layer disposed over the gate electrode stack, a pair of low doping drain (LDD) regions disposed in the substrate such that the formed LDD regions are disposed adjacent to the gate electrode stack and are disposed apart from each other at opposite sides of the gate electrode stack, and a first spacer layer disposed around the gate electrode stack such that the disposed first spacer layer together with the disposed protective cap layer covers the gate electrode stack, wherein the first spacer layer is an oxide layer, comprising: removing a first layer in the substrate by etching the substrate to expose a sidewall in the LDD regions and under the first spacer layer, to further expose the substrate around the gate electrode stack to form source and drain regions adjacent to the exposed LDD regions; forming a second spacer layer over the first spacer layer such that the formed second spacer layer extends from the exposed source and drain regions; removing a second layer in the substrate around the formed second spacer layer and the source and drain regions to further expose the substrate around the LDD regions such that the exposed substrate extends the formed sidewall in the LDD regions further into the substrate to form recesses in the source and drain regions; forming an oxide layer over the exposed substrate in the formed source and drain recesses such that the formed second spacer layer together with the formed oxide layer closes the exposed LDD regions; removing the second spacer layer by selective etching to expose the closed LDD regions; removing the formed oxide layer from the source and drain regions by oxide spacer etching to expose the substrate in the source and drain regions and to leave a portion or the oxide layer in the recesses to form a dielectric plug in each of the recess and surround a channel region between the source and drain regions; and depositing epitaxial silicon in the source and drain recesses such that the deposited epitaxial silicon fills the recesses to form the source and drain regions, and to connect the channel and the source and drain regions.

Claim 25

A method of fabricating a short-channel Metal-Oxide-Silicon Field Effect Transistor (MOSFET) device on a substrate including an active region surrounded by an isolation region, a gate electrode stack disposed over the active region, a protective cap layer disposed over the gate electrode stack, a pair of low doping drain (LDD) regions disposed in the substrate such that the formed LDD regions are disposed adjacent to the gate electrode stack and are disposed apart from each other at opposite sides of the gate electrode stack, and a first spacer layer disposed around the gate electrode stack such that the disposed first spacer layer together with the disposed protective cap layer covers the gate electrode stack, wherein the first spacer layer is an oxide layer, comprising: removing a first layer in the substrate by etching the substrate to expose a sidewall in the LDD regions and under the first spacer layer, to further expose the substrate around the gate electrode stack to form source and drain regions adjacent to the exposed LDD regions; forming a second spacer layer over the first spacer layer such that the formed second spacer layer extends from the exposed source and drain regions; removing a second layer in the substrate around the formed second spacer layer and the source and drain regions to further expose the substrate around the LDD regions such that the exposed substrate extends the formed sidewall in the LDD regions further into the substrate to form recesses in the source and drain regions; forming an oxide layer over the exposed substrate in the formed source and drain recesses such that the formed second spacer layer together with the formed oxide layer closes the exposed LDD regions; removing the second spacer layer by selective etching to expose the closed LDD regions; removing the formed oxide layer from the source and drain regions by oxide spacer etching to expose the substrate in the source and drain regions and to leave a portion or the oxide layer in the recesses to form a dielectric plug in each of the recess and surround a channel region between the source and drain regions; and depositing epitaxial silicon in the source and drain recesses such that the deposited epitaxial silicon fills the recesses to form the source and drain regions, and to connect the channel and the source and drain regions.

Claim 29

A method of fabricating a semiconductor device, comprising: providing a substrate including an active region surrounded by an isolation region, and a gate electrode stack disposed over the active region; forming a protective cap layer over the gate electrode stack; forming a pair of low doping drain (LDD) regions by implanting a dopant into the substrate such that the formed LDD regions are disposed adjacent to the gate electrode stack and are disposed apart from each other at opposite sides of the gate electrode stack; forming a first spacer layer around the gate electrode stack and such that the formed first spacer layer together with the formed protective cap layer covers the gate electrode stack; removing a first layer in the substrate by etching the substrate to expose a sidewall in the LDD regions and under the first spacer layer to further expose the substrate around the gate electrode stack to form source and drain regions adjacent to the exposed LDD regions; forming a second spacer layer over the first spacer layer such that the formed second spacer layer extends from the exposed source and drain regions; removing a second layer in the substrate around the formed second spacer layer and the source and drain regions to further expose the substrate around the LDD regions such that the exposed substrate extends the formed sidewall in the LDD regions further into the substrate to form recesses in the source and drain regions; forming an oxide layer over the exposed substrate in the formed source and drain recesses such that the formed second spacer layer together with the formed oxide layer closes the exposed LDD regions; removing the second spacer layer by selective etching to expose the closed LDD regions; removing the formed oxide layer from the source and drain regions by oxide spacer etching to expose the substrate in the source and drain regions and to leave a portion of the oxide layer in the recesses to form a dielectric spacer in each of the recess and surround a channel region between the source and drain regions; and depositing epitaxial silicon on the exposed substrate such that the deposited epitaxial silicon fills the formed recesses in the source and drain regions to create a connection between the channel and the filled source and drain regions.

Claim 30

A method of fabricating a semiconductor device, comprising: providing a substrate including an active region surrounded by an isolation region, and a gate electrode stack disposed over the active region; forming a protective cap layer over the gate electrode stack; forming a pair of low doping drain (LDD) regions by implanting a dopant into the substrate such that the formed LDD regions are disposed adjacent to the gate electrode stack and are disposed apart from each other at opposite sides of the gate electrode stack; forming a first spacer layer around the gate electrode stack and such that the formed first spacer layer together with the formed protective cap layer covers the gate electrode stack; removing a first layer in the substrate by etching the substrate to expose a sidewall in the LDD regions and under the first spacer layer to further expose the substrate around the gate electrode stack to form source and drain regions adjacent to the exposed LDD regions; forming a second spacer layer over the first spacer layer such that the formed second spacer layer extends from the exposed source and drain regions; removing a second layer in the substrate around the formed second spacer layer and the source and drain regions to further expose the substrate around the LDD regions such that the exposed substrate extends the formed sidewall in the LDD regions further into the substrate to form recesses in the source and drain regions; forming an oxide layer over the exposed substrate in the formed source and drain recesses such that the formed second spacer layer together with the formed oxide layer closes the exposed LDD regions; removing the second spacer layer by selective etching to expose the closed LDD regions; removing the formed oxide layer from the source and drain regions by oxide spacer etching to expose the substrate in the source and drain regions and to leave a portion of the oxide layer in the recesses to form a dielectric spacer in each of the recess and surround a channel region between the source and drain regions; and depositing epitaxial silicon on the exposed substrate such that the deposited epitaxial silicon fills the formed recesses in the source and drain regions to create a connection between the channel and the filled source and drain regions.

Claim 34

A method of fabricating a semiconductor device, comprising: providing a substrate including an active region surrounded by an isolation region, and a gate electrode stack disposed over the active region; forming a protective cap layer over the gate electrode stack from a dielectric material; forming a pair of low doping drain (LDD) regions by implanting a dopant into the substrate such that the formed LDD regions are disposed adjacent to the gate electrode stack and are disposed apart from each other at opposite sides of the gate electrode stack; forming a first spacer layer around the gate electrode stack and such that the formed first spacer layer together with the formed protective cap layer covers the gate electrode stack; removing a first layer in the substrate by etching the substrate to expose a sidewall in the LDD regions and under the first spacer layer to further expose the substrate around the gate electrode stack to form source and drain regions adjacent to the exposed LDD regions; forming a second spacer layer over the first spacer layer such that the formed second spacer layer extends from the exposed source and drain regions; removing a second layer in the substrate around the formed second spacer layer and the source and drain regions to further expose the substrate around the LDD regions such that the exposed substrate extends the formed sidewall in the LDD regions further into the substrate to form recesses in the source and drain regions; forming an oxide layer over the exposed substrate in the formed source and drain recesses such that the formed second spacer layer together with the formed oxide layer closes the exposed LDD regions; removing the second spacer layer by selective etching to expose the closed LDD regions; removing the formed oxide layer from the source and drain regions by oxide spacer etching to expose the substrate in the source and drain regions and to leave a portion of the oxide layer in the recesses to form a dielectric spacer in each of the recess and surround a channel region between the source and drain regions; and depositing epitaxial silicon on the exposed substrate such that the deposited epitaxial silicon fills the formed recesses in the source and drain regions to create a connection between the channel and the filled source and drain regions.

Claim 35

A method of fabricating a semiconductor device, comprising: providing a substrate including an active region surrounded by an isolation region, and a gate electrode stack disposed over the active region; forming a protective cap layer over the gate electrode stack from a dielectric material; forming a pair of low doping drain (LDD) regions by implanting a dopant into the substrate such that the formed LDD regions are disposed adjacent to the gate electrode stack and are disposed apart from each other at opposite sides of the gate electrode stack; forming a first spacer layer around the gate electrode stack and such that the formed first spacer layer together with the formed protective cap layer covers the gate electrode stack; removing a first layer in the substrate by etching the substrate to expose a sidewall in the LDD regions and under the first spacer layer to further expose the substrate around the gate electrode stack to form source and drain regions adjacent to the exposed LDD regions; forming a second spacer layer over the first spacer layer such that the formed second spacer layer extends from the exposed source and drain regions; removing a second layer in the substrate around the formed second spacer layer and the source and drain regions to further expose the substrate around the LDD regions such that the exposed substrate extends the formed sidewall in the LDD regions further into the substrate to form recesses in the source and drain regions; forming an oxide layer over the exposed substrate in the formed source and drain recesses such that the formed second spacer layer together with the formed oxide layer closes the exposed LDD regions; removing the second spacer layer by selective etching to expose the closed LDD regions; removing the formed oxide layer from the source and drain regions by oxide spacer etching to expose the substrate in the source and drain regions and to leave a portion of the oxide layer in the recesses to form a dielectric spacer in each of the recess and surround a channel region between the source and drain regions; and depositing epitaxial silicon on the exposed substrate such that the deposited epitaxial silicon fills the formed recesses in the source and drain regions to create a connection between the channel and the filled source and drain regions.

Claim 39

A method of fabricating a short-channel MOSFET, comprising: providing a substrate including an active region surrounded by an isolation region, and a gate electrode stack disposed over the active region; forming a protective cap layer over the gate electrode stack; forming a first spacer layer around the gate electrode stack and such that the formed first spacer layer together with the formed protective cap layer covers the gate electrode stack; removing a first layer in the substrate by etching the substrate to expose the substrate to form source and drain regions such that the formed source and drain regions are disposed adjacent to the gate electrode stack and apart from each other at opposite sides of the gate electrode stack; forming a second spacer layer over the formed first spacer layer such that the formed second spacer layer extends from the exposed source and drain regions; removing a second layer in the substrate around the formed second spacer layer and the source and drain regions and to further expose the substrate to form a sidewall in the substrate and a recess for the source and drain regions; forming an oxide layer over the exposed substrate in the formed source and drain recesses such that the formed second spacer layer and the oxide layer close the sidewalls; removing the second spacer layer by selective etching to expose the first spacer layer, removing the formed oxide layer from the source and drain regions by oxide spacer etching to expose the substrate in the source and drain regions and to leave a portion of the oxide layer in the recesses to form a dielectric spacer in each of the recess and surround a channel region between the source and drain regions; depositing epitaxial silicon on the exposed substrate such that the deposited epitaxial silicon fills the formed recesses in the source and drain regions to create a connection between the channel region and the filled source and drain regions; etching back a portion of the first spacer layer around the source and drain regions to form exposed silicon regions such that the exposed silicon regions are disposed adjacent to the gate electrode stack and the source and drain regions; implanting the exposed silicon regions with a dopant to form LDD regions such that the formed LDD regions connect the channel region and the source and drain regions; and forming a third spacer layer over the gate electrode stack.

Claim 40

A method of fabricating a short-channel MOSFET, comprising: providing a substrate including an active region surrounded by an isolation region, and a gate electrode stack disposed over the active region; forming a protective cap layer over the gate electrode stack; forming a first spacer layer around the gate electrode stack and such that the formed first spacer layer together with the formed protective cap layer covers the gate electrode stack; removing a first layer in the substrate by etching the substrate to expose the substrate to form source and drain regions such that the formed source and drain regions are disposed adjacent to the gate electrode stack and apart from each other at opposite sides of the gate electrode stack; forming a second spacer layer over the formed first spacer layer such that the formed second spacer layer extends from the exposed source and drain regions; removing a second layer in the substrate around the formed second spacer layer and the source and drain regions and to further expose the substrate to form a sidewall in the substrate and a recess for the source and drain regions; forming an oxide layer over the exposed substrate in the formed source and drain recesses such that the formed second spacer layer and the oxide layer close the sidewalls; removing the second spacer layer by selective etching to expose the first spacer layer, removing the formed oxide layer from the source and drain regions by oxide spacer etching to expose the substrate in the source and drain regions and to leave a portion of the oxide layer in the recesses to form a dielectric spacer in each of the recess and surround a channel region between the source and drain regions; depositing epitaxial silicon on the exposed substrate such that the deposited epitaxial silicon fills the formed recesses in the source and drain regions to create a connection between the channel region and the filled source and drain regions; etching back a portion of the first spacer layer around the source and drain regions to form exposed silicon regions such that the exposed silicon regions are disposed adjacent to the gate electrode stack and the source and drain regions; implanting the exposed silicon regions with a dopant to form LDD regions such that the formed LDD regions connect the channel region and the source and drain regions; and forming a third spacer layer over the gate electrode stack.

Claim 44

A method or fabricating a short-channel MOSFET, comprising; providing a substrate including an active region surrounded by an isolation region, and a gate electrode stack disposed over the active region; forming a dielectric protective cap layer over the gate electrode stack; forming a first spacer layer around the gate electrode stack and such that the formed first spacer layer together with the formed protective cap layer covers the gate electrode stack; removing a first layer in the substrate by etching the substrate to expose the substrate to form source and drain regions such that the formed source and drain regions are disposed adjacent to the gate electrode stack and apart from each other at opposite sides of the gate electrode stack; forming a second spacer layer over the formed first spacer layer such that the formed second spacer layer extends from the exposed source and drain regions; removing a second layer in the substrate around the formed second spacer layer and the source and drain regions and to further expose the substrate to form a sidewall in the substrate and a recess for the source and drain regions; forming an oxide layer over the exposed substrate in the formed source and drain recesses such that the formed second spacer layer and the oxide layer close the sidewalls; removing the second spacer layer by selective etching to expose the first spacer layer; removing the formed oxide layer from the source and drain regions by oxide spacer etching to expose the substrate in the source and drain regions and to leave a portion of the oxide layer in the recesses to form a dielectric spacer in each of the recess and surround a channel region between the source and drain regions; depositing epitaxial silicon on the exposed substrate such that the deposited epitaxial silicon fills the formed recesses in the source and drain regions to create a connection between the channel region and the filled source and drain regions; etching back a portion of the first spacer layer around the source and drain regions to form exposed silicon regions such that the exposed silicon regions are disposed adjacent to the gate electrode stack and the source and drain regions; implanting the exposed silicon regions with a dopant to form LDD regions such that the formed LDD regions connect the channel region and the source and drain regions; and forming a third spacer layer over the gate electrode stack using chemical vapor deposition followed by dry etching.

Claim 45

A method or fabricating a short-channel MOSFET, comprising; providing a substrate including an active region surrounded by an isolation region, and a gate electrode stack disposed over the active region; forming a dielectric protective cap layer over the gate electrode stack; forming a first spacer layer around the gate electrode stack and such that the formed first spacer layer together with the formed protective cap layer covers the gate electrode stack; removing a first layer in the substrate by etching the substrate to expose the substrate to form source and drain regions such that the formed source and drain regions are disposed adjacent to the gate electrode stack and apart from each other at opposite sides of the gate electrode stack; forming a second spacer layer over the formed first spacer layer such that the formed second spacer layer extends from the exposed source and drain regions; removing a second layer in the substrate around the formed second spacer layer and the source and drain regions and to further expose the substrate to form a sidewall in the substrate and a recess for the source and drain regions; forming an oxide layer over the exposed substrate in the formed source and drain recesses such that the formed second spacer layer and the oxide layer close the sidewalls; removing the second spacer layer by selective etching to expose the first spacer layer; removing the formed oxide layer from the source and drain regions by oxide spacer etching to expose the substrate in the source and drain regions and to leave a portion of the oxide layer in the recesses to form a dielectric spacer in each of the recess and surround a channel region between the source and drain regions; depositing epitaxial silicon on the exposed substrate such that the deposited epitaxial silicon fills the formed recesses in the source and drain regions to create a connection between the channel region and the filled source and drain regions; etching back a portion of the first spacer layer around the source and drain regions to form exposed silicon regions such that the exposed silicon regions are disposed adjacent to the gate electrode stack and the source and drain regions; implanting the exposed silicon regions with a dopant to form LDD regions such that the formed LDD regions connect the channel region and the source and drain regions; and forming a third spacer layer over the gate electrode stack using chemical vapor deposition followed by dry etching.

Claim 49

A method of fabricating a memory circuit including a short-channel MOSFET, comprising: providing a semiconductor substrate including an active region surrounded by an isolation region, and a gate electrode stack disposed over the active region; forming a protective cap layer over the gate electrode stack; forming a pair of low doping drain (LDD) regions by implanting a dopant into the substrate such that the formed LDD regions are disposed adjacent to the gate electrode stack and are disposed apart from each other at opposite sides of the gate electrode stack; forming a first spacer layer around the gate electrode stack and such that the formed first spacer layer together with the formed protective cap layer covers the gate electrode stack; removing a first layer in the substrate by etching the substrate to expose a sidewall in the LDD regions and under the first spacer layer to further expose the substrate around the gate electrode stack to form source and drain regions adjacent to the exposed LDD regions; forming a second spacer layer over the first spacer layer such that the formed second spacer layer extends from the exposed source and drain regions; removing a second layer in the substrate around the formed second spacer layer and the source and drain regions to further expose the substrate around the LDD regions such that the exposed substrate extends the formed sidewall in the LDD regions further into the substrate to form recesses in the source and drain regions; forming an oxide layer over the exposed substrate in the formed source and drain recesses such that the formed second spacer layer together with the formed oxide layer closes the exposed LDD regions; removing the second spacer layer by selective etching to expose the closed LDD regions; removing the formed oxide layer from the source and drain regions by oxide spacer etching to expose the substrate in the source and drain regions and to leave a portion of the oxide layer in the recesses to form a dielectric spacer in each of the recess and surround a channel region between the source and drain regions; and depositing epitaxial silicon on the exposed substrate such that the deposited epitaxial silicon fills the formed recesses in the source and drain regions to create a connection between the channel and the filled source and drain regions.

Claim 50

A method of fabricating a memory circuit including a short-channel MOSFET, comprising: providing a semiconductor substrate including an active region surrounded by an isolation region, and a gate electrode stack disposed over the active region; forming a protective cap layer over the gate electrode stack; forming a pair of low doping drain (LDD) regions by implanting a dopant into the substrate such that the formed LDD regions are disposed adjacent to the gate electrode stack and are disposed apart from each other at opposite sides of the gate electrode stack; forming a first spacer layer around the gate electrode stack and such that the formed first spacer layer together with the formed protective cap layer covers the gate electrode stack; removing a first layer in the substrate by etching the substrate to expose a sidewall in the LDD regions and under the first spacer layer to further expose the substrate around the gate electrode stack to form source and drain regions adjacent to the exposed LDD regions; forming a second spacer layer over the first spacer layer such that the formed second spacer layer extends from the exposed source and drain regions; removing a second layer in the substrate around the formed second spacer layer and the source and drain regions to further expose the substrate around the LDD regions such that the exposed substrate extends the formed sidewall in the LDD regions further into the substrate to form recesses in the source and drain regions; forming an oxide layer over the exposed substrate in the formed source and drain recesses such that the formed second spacer layer together with the formed oxide layer closes the exposed LDD regions; removing the second spacer layer by selective etching to expose the closed LDD regions; removing the formed oxide layer from the source and drain regions by oxide spacer etching to expose the substrate in the source and drain regions and to leave a portion of the oxide layer in the recesses to form a dielectric spacer in each of the recess and surround a channel region between the source and drain regions; and depositing epitaxial silicon on the exposed substrate such that the deposited epitaxial silicon fills the formed recesses in the source and drain regions to create a connection between the channel and the filled source and drain regions.

Claim 54

A method of fabricating a memory circuit including a short-channel MOSFET, comprising: providing a semiconductor substrate including an active region surround by an isolation region, and a gate electrode stack disposed over the active region; forming a dielectric protective cap layer over the gate electrode stack; forming a pair of low doping drain (LDD) regions by implanting a dopant into the substrate such that the formed LDD regions are disposed adjacent to the gate electrode stack and are disposed apart from each other at opposite sides of the gate electrode stack; forming a first spacer layer around the gate electrode stack and such that the formed first spacer layer together with the formed protective cap layer covers the gate electrode stack; removing a first layer in the substrate by etching the substrate to expose a sidewall in the LDD regions under the first spacer layer using etching selective to silicon to further expose the substrate around the gate electrode stack to form source and drain regions adjacent to the exposed LDD regions; forming a second spacer layer over the first spacer layer such that the formed second spacer layer extends from the exposed source and drain regions; removing a second layer in the substrate around the formed second spacer layer and the source and drain regions to further expose the substrate around the LDD regions such that the exposed substrate extends the formed sidewall in the LDD regions further into the substrate to form recesses in the source and drain regions; forming an oxide layer over the exposed substrate in the formed source and drain recesses such that the formed second spacer layer together with the farmed oxide layer closes the exposed LDD regions; removing the second spacer layer by selective etching to expose the closed LDD regions; removing the formed oxide layer from the source and drain regions by oxide spacer etching to expose the substrate in the source and drain regions and to leave a portion of the oxide layer in the recesses to form a dielectric spacer in each of the recess and surround a channel region between the source and drain regions; and depositing epitaxial silicon on the exposed substrate such that the deposited epitaxial silicon fills the formed recesses in the source and drain regions to create a connection between the channel and the filled source and drain regions.

Claim 55

A method of fabricating a memory circuit including a short-channel MOSFET, comprising: providing a semiconductor substrate including an active region surround by an isolation region, and a gate electrode stack disposed over the active region; forming a dielectric protective cap layer over the gate electrode stack; forming a pair of low doping drain (LDD) regions by implanting a dopant into the substrate such that the formed LDD regions are disposed adjacent to the gate electrode stack and are disposed apart from each other at opposite sides of the gate electrode stack; forming a first spacer layer around the gate electrode stack and such that the formed first spacer layer together with the formed protective cap layer covers the gate electrode stack; removing a first layer in the substrate by etching the substrate to expose a sidewall in the LDD regions under the first spacer layer using etching selective to silicon to further expose the substrate around the gate electrode stack to form source and drain regions adjacent to the exposed LDD regions; forming a second spacer layer over the first spacer layer such that the formed second spacer layer extends from the exposed source and drain regions; removing a second layer in the substrate around the formed second spacer layer and the source and drain regions to further expose the substrate around the LDD regions such that the exposed substrate extends the formed sidewall in the LDD regions further into the substrate to form recesses in the source and drain regions; forming an oxide layer over the exposed substrate in the formed source and drain recesses such that the formed second spacer layer together with the farmed oxide layer closes the exposed LDD regions; removing the second spacer layer by selective etching to expose the closed LDD regions; removing the formed oxide layer from the source and drain regions by oxide spacer etching to expose the substrate in the source and drain regions and to leave a portion of the oxide layer in the recesses to form a dielectric spacer in each of the recess and surround a channel region between the source and drain regions; and depositing epitaxial silicon on the exposed substrate such that the deposited epitaxial silicon fills the formed recesses in the source and drain regions to create a connection between the channel and the filled source and drain regions.

Claim 59

A method of fabricating a logic circuit including a short-channel Metal-Oxide-Silicon Field Effect Transistor (MOSFET) device, comprising: providing a substrate including an active region surrounded by an isolation region, a gate electrode stack disposed over the active region, a dielectric protective cap layer disposed over the gate electrode stack, a pair of low doping drain (LDD) regions disposed in the substrate such that the formed LDD regions are disposed adjacent to the gate electrode stack and are disposed apart from each other at opposite sides of the gate electrode stack, and a first spacer layer disposed around the gate electrode stack such that the disposed first spacer layer together with the disposed protective cap layer covers the gate electrode stack; removing a first layer in the substrate by etching the substrate to expose a sidewall in the LDD regions and under the first spacer layer to further expose the substrate around the gate electrode stack to form source and drain regions adjacent to the exposed LDD regions; forming a second spacer layer over the first spacer layer such that the formed second spacer layer extends from the exposed source and drain regions; removing a second layer in the substrate around the formed second spacer layer and the source and drain regions to further expose the substrate around the LDD regions such that the exposed substrate extends the formed sidewall in the LDD regions further into the substrate to form recesses in the source and drain regions; forming an oxide layer over the exposed substrate in the formed source and drain reassess such that the formed second spacer layer together with the formed oxide layer closes the exposed LDD regions; removing the second spacer layer by selective etching to expose the closed LDD regions; removing the formed oxide layer from the source and drain regions by oxide spacer etching to expose the substrate in the source and drain regions and to leave a portion of the oxide layer in the recesses to form a dielectric spacer in each of the recess and surround a channel region between the source and drain regions; and depositing epitaxial silicon on the exposed substrate such that the deposited epitaxial silicon fills the formed recesses in the source and drain regions to create a connection between the channel and the filled source and drain regions.

Claim 60

A method of fabricating a logic circuit including a short-channel Metal-Oxide-Silicon Field Effect Transistor (MOSFET) device, comprising: providing a substrate including an active region surrounded by an isolation region, a gate electrode stack disposed over the active region, a dielectric protective cap layer disposed over the gate electrode stack, a pair of low doping drain (LDD) regions disposed in the substrate such that the formed LDD regions are disposed adjacent to the gate electrode stack and are disposed apart from each other at opposite sides of the gate electrode stack, and a first spacer layer disposed around the gate electrode stack such that the disposed first spacer layer together with the disposed protective cap layer covers the gate electrode stack; removing a first layer in the substrate by etching the substrate to expose a sidewall in the LDD regions and under the first spacer layer to further expose the substrate around the gate electrode stack to form source and drain regions adjacent to the exposed LDD regions; forming a second spacer layer over the first spacer layer such that the formed second spacer layer extends from the exposed source and drain regions; removing a second layer in the substrate around the formed second spacer layer and the source and drain regions to further expose the substrate around the LDD regions such that the exposed substrate extends the formed sidewall in the LDD regions further into the substrate to form recesses in the source and drain regions; forming an oxide layer over the exposed substrate in the formed source and drain reassess such that the formed second spacer layer together with the formed oxide layer closes the exposed LDD regions; removing the second spacer layer by selective etching to expose the closed LDD regions; removing the formed oxide layer from the source and drain regions by oxide spacer etching to expose the substrate in the source and drain regions and to leave a portion of the oxide layer in the recesses to form a dielectric spacer in each of the recess and surround a channel region between the source and drain regions; and depositing epitaxial silicon on the exposed substrate such that the deposited epitaxial silicon fills the formed recesses in the source and drain regions to create a connection between the channel and the filled source and drain regions.

Claim 66

A method of fabricating a short-channel MOSFET, comprising: providing a substrate including an active region surrounded by an isolation region, and a gate electrode stack disposed over the active region; forming a protective cap layer over the gate electrode stack; forming a first spacer layer around the gate electrode stack and such that the formed first spacer layer together with the formed protective cap layer covers the gate electrode stack; removing a first layer in the substrate by etching the substrate to expose the substrate to form source and drain regions such that the formed source and drain regions are disposed adjacent to the gate electrode stack and apart from each other at opposite sides of the gate electrode stack; forming a second spacer layer over the formed first spacer layer such that the formed second spacer layer extends from the exposed source and drain regions; removing a second layer in the substrate around the formed second spacer layer and the source and drain regions to further expose the substrate to form a sidewall in the substrate and a recess for the source and drain regions; forming an oxide layer over the exposed substrate in the formed source and drain recesses such that the formed second spacer layer and the oxide layer close the sidewalls; removing the formed oxide layer from the source and drain regions by oxide spacer etching to expose the substrate in the source and drain regions and to leave a portion of the oxide layer in the recesses to form a dielectric spacer in each of the recess and surround a channel region between the source and drain regions; removing the second spacer layer by selective etching to expose the first spacer layer; depositing epitaxial silicon on the exposed substrate such that the deposited epitaxial silicon fills the formed recesses in the source and drain regions to create a connection between the channel region and the filled source and drain regions; etching back a portion of the first spacer layer around the source and drain regions to form exposed silicon regions such that the exposed silicon regions are disposed adjacent to the gate electrode stack and the source and drain regions; implanting the exposed silicon regions with a dopant to form a LDD region, wherein the formed LDD region connects the channel region and the source and drain regions; and forming a third spacer layer over the gate electrode stack.

Claim 67

A method of fabricating a short-channel MOSFET, comprising: providing a substrate including an active region surrounded by an isolation region, and a gate electrode stack disposed over the active region; forming a protective cap layer over the gate electrode stack; forming a first spacer layer around the gate electrode stack and such that the formed first spacer layer together with the formed protective cap layer covers the gate electrode stack; removing a first layer in the substrate by etching the substrate to expose the substrate to form source and drain regions such that the formed source and drain regions are disposed adjacent to the gate electrode stack and apart from each other at opposite sides of the gate electrode stack; forming a second spacer layer over the formed first spacer layer such that the formed second spacer layer extends from the exposed source and drain regions; removing a second layer in the substrate around the formed second spacer layer and the source and drain regions to further expose the substrate to form a sidewall in the substrate and a recess for the source and drain regions; forming an oxide layer over the exposed substrate in the formed source and drain recesses such that the formed second spacer layer and the oxide layer close the sidewalls; removing the formed oxide layer from the source and drain regions by oxide spacer etching to expose the substrate in the source and drain regions and to leave a portion of the oxide layer in the recesses to form a dielectric spacer in each of the recess and surround a channel region between the source and drain regions; removing the second spacer layer by selective etching to expose the first spacer layer; depositing epitaxial silicon on the exposed substrate such that the deposited epitaxial silicon fills the formed recesses in the source and drain regions to create a connection between the channel region and the filled source and drain regions; etching back a portion of the first spacer layer around the source and drain regions to form exposed silicon regions such that the exposed silicon regions are disposed adjacent to the gate electrode stack and the source and drain regions; implanting the exposed silicon regions with a dopant to form a LDD region, wherein the formed LDD region connects the channel region and the source and drain regions; and forming a third spacer layer over the gate electrode stack.

Claim 69

A method of fabricating a short-channel Metal-Oxide-Silicon Field Effect Transistor (MOSFET) device, comprising: providing a substrate including an active region surrounded by an isolation region, a gate electrode stack disposed over the active region, a protective cap layer disposed over the gate electrode stack, a protective cap layer disposed over the gate electrode stack, a pair of low doping drain (LDD) regions disposed in the substrate such that the formed LDD regions are disposed adjacent to the gate electrode stack and are disposed apart from each other at opposite sides of the gate electrode stack, and a first spacer layer disposed around the gate electrode stack such that the disposed first spacer layer together with the disposed protective cap layer encloses the gate electrode stack; removing a first layer in the substrate by etching the substrate to expose a sidewall in the LDD regions and under the first spacer layer to further expose the substrate around the gate electrode stack to form source and drain regions adjacent to the exposed LDD regions; forming a second spacer layer over the first spacer layer such that the formed second spacer layer extends from the exposed source and drain regions; removing a second layer in the substrate around the formed second spacer layer and the source and drain regions to further expose the substrate around the LDD regions such that the exposed substrate extends the formed sidewall in the LDD regions further into the substrate to form recesses in the source and drain regions; forming an oxide layer over the exposed substrate in the formed source and drain recesses such that the formed second spacer layer together with the formed oxide layer closes the exposed LDD regions; removing the second spacer layer by selective etching to expose the closed LDD regions; and removing the formed oxide layer from the source and drain recesses by oxide spacer etching to expose the substrate in the source and drain regions and to leave a portion of the oxide layer in the recesses to form a dielectric spacer in each of the recess and surround a channel region between the source and drain regions.

Claim 70

A method of fabricating a short-channel Metal-Oxide-Silicon Field Effect Transistor (MOSFET) device, comprising: providing a substrate including an active region surrounded by an isolation region, a gate electrode stack disposed over the active region, a protective cap layer disposed over the gate electrode stack, a protective cap layer disposed over the gate electrode stack, a pair of low doping drain (LDD) regions disposed in the substrate such that the formed LDD regions are disposed adjacent to the gate electrode stack and are disposed apart from each other at opposite sides of the gate electrode stack, and a first spacer layer disposed around the gate electrode stack such that the disposed first spacer layer together with the disposed protective cap layer encloses the gate electrode stack; removing a first layer in the substrate by etching the substrate to expose a sidewall in the LDD regions and under the first spacer layer to further expose the substrate around the gate electrode stack to form source and drain regions adjacent to the exposed LDD regions; forming a second spacer layer over the first spacer layer such that the formed second spacer layer extends from the exposed source and drain regions; removing a second layer in the substrate around the formed second spacer layer and the source and drain regions to further expose the substrate around the LDD regions such that the exposed substrate extends the formed sidewall in the LDD regions further into the substrate to form recesses in the source and drain regions; forming an oxide layer over the exposed substrate in the formed source and drain recesses such that the formed second spacer layer together with the formed oxide layer closes the exposed LDD regions; removing the second spacer layer by selective etching to expose the closed LDD regions; and removing the formed oxide layer from the source and drain recesses by oxide spacer etching to expose the substrate in the source and drain regions and to leave a portion of the oxide layer in the recesses to form a dielectric spacer in each of the recess and surround a channel region between the source and drain regions.