Patent US6807663B2 successfully refreshed from Google Patents.
US6807663B2
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Accelerated layout processing using OPC pre-processing
Assignee: Synopsys Inc
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Filing: 2002-09-23
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Granted: 2004-10-19
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Expires: 2022-09-23
Abstract
Abstract Performing optical proximity correction (OPC) is typically done during a critical time, wherein even small delays in finishing OPC can have significant adverse effects on product introduction and/or market exposure. In accordance with one feature of the invention, sets of repeating structures in library elements and/or layout data can be identified during a non-critical time, e.g. early in cell library development, possibly years prior to the direct application of OPC to a final layout. OPC can be performed on repeating structures during this non-critical time. Later, during the critical time (e.g. during tape out), an OPC tool can use the pre-processed structures in conjunction with a chip layout to more quickly generate a modified layout, thereby saving valuable time as a chip moves from design to production.
Inventors
- 👤 Michel Luc Côté
- 👤 Christophe Pierrat
- 👤 Philippe Hurat
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 10:46
CPC Classifications
G; G03; G03F; G03F1/00; G03F1/36; G06; G06F; G06F30/00; G06F30/30; G06F30/39
Claims Analysis
Total Claims: 30
Claim 1
Independent Claim
75 words
A method of minimizing time for performing optical proximity correction (OPC) on a chip layout, the method comprising: identifying a set of repeating structures within defined design units, each instance of the repeating structures having substantially the same proximity effect environment within a predetermined distance; pre-processing a representative repeating structure in the set of repeating structures during a non-critical time in chip design; and based on the pre-processing, performing the OPC on the chip layout.
Claim 2
Independent Claim
75 words
A method of minimizing time for performing optical proximity correction (OPC) on a chip layout, the method comprising: identifying a set of repeating structures within defined design units, each instance of the repeating structures having substantially the same proximity effect environment within a predetermined distance; pre-processing a representative repeating structure in the set of repeating structures during a non-critical time in chip design; and based on the pre-processing, performing the OPC on the chip layout.
Claim 3
Dependent Claim
15 words
The method of claim 1 , wherein identifying includes accessing a library of standard cells.
Claim 4
Dependent Claim
12 words
The method of claim 1 , wherein identifying includes receiving layout data.
Claim 5
Dependent Claim
42 words
The method of claim 1 , wherein a defined design unit includes at least one of: a standard cell, an inner core of a standard cell, a memory cell, an input/output pad, an IP core, a data path, and a custom block.
Claim 6
Dependent Claim
14 words
The method of claim 1 , wherein pre-processing is performed only on static structures.
Claim 7
Dependent Claim
16 words
The method of claim 1 , wherein the non-critical time is after identifying but before OPC.
Claim 8
Dependent Claim
18 words
The method of claim 1 , further including instantiating structures in the set of repeating structures before OPC.
Claim 9
Dependent Claim
35 words
The method of claim 1 , wherein results of the pre-processing include at least one of dissection and evaluation points for segments, contrast images at the evaluation points, and corrected versions of the repeating structures.
Claim 10
Dependent Claim
18 words
The method of claim 1 , wherein the predetermined distance is a function of the proximity effect range.
Claim 11
Independent Claim
65 words
A method of designing a library of standard cells, the method comprising: identifying repeating structures in at least one of the standard cells, wherein a set of repeating structures has substantially the same proximity effect environment within a predetermined range; pre-processing one of the set of repeating structures for optical proximity correction during a non-critical time in chip design; and storing results of the pre-processing.
Claim 12
Independent Claim
65 words
A method of designing a library of standard cells, the method comprising: identifying repeating structures in at least one of the standard cells, wherein a set of repeating structures has substantially the same proximity effect environment within a predetermined range; pre-processing one of the set of repeating structures for optical proximity correction during a non-critical time in chip design; and storing results of the pre-processing.
Claim 13
Dependent Claim
30 words
The method of claim 10 , wherein identifying can be done during creation of the standard cells, wherein the standard cells are optimized to maximize the occurrence of repeating structures.
Claim 14
Dependent Claim
22 words
The method of claim 10 , wherein repeating structures can include at least one of segments, shapes, polygons, and groups of polygons.
Claim 15
Dependent Claim
38 words
The method of claim 10 , wherein repeating structures can be grouped in the cores of the standard cells and other structures less static than the repeating structures can be placed in the perimeters of the standard cells.
Claim 16
Dependent Claim
36 words
The method of claim 10 , wherein the results of the pre-processing include at least one of dissection and evaluation points for segments, contrast images at the evaluation points, and corrected versions of the repeating structures.
Claim 17
Dependent Claim
18 words
The method of claim 10 , wherein storing the results can be done within a standard cell layout.
Claim 18
Dependent Claim
26 words
The method of claim 15 , wherein the standard cell layout includes hierarchical data and the results are stored on a layer of the hierarchical data.
Claim 19
Dependent Claim
30 words
The method of claim 15 , wherein the standard cell layout includes hierarchical data and the results are stored on a layer of the hierarchical data dedicated to the results.
Claim 20
Dependent Claim
20 words
The method of claim 10 , wherein storing the results can include a separate data file associated with the library.
Claim 21
Dependent Claim
21 words
The method of claim 10 , wherein the standard cells and the results of the pre-processing are provided in GDS-II format.
Claim 22
Dependent Claim
71 words
A storage means accessible by an optical proximity correction (OPC) tool, the storage means including: pre-processed structures associated with a plurality of design units, wherein the pre-processed structures were created during a non-critical time in chip design, wherein each set of pre-processed structures has at least substantially the same proximity effect environment within a predetermined distance, and wherein the pre-processed structures can be used to perform OPC on a chip layout.
Claim 23
Dependent Claim
71 words
A storage means accessible by an optical proximity correction (OPC) tool, the storage means including: pre-processed structures associated with a plurality of design units, wherein the pre-processed structures were created during a non-critical time in chip design, wherein each set of pre-processed structures has at least substantially the same proximity effect environment within a predetermined distance, and wherein the pre-processed structures can be used to perform OPC on a chip layout.
Claim 24
Dependent Claim
14 words
The storage means of claim 20 provided within at least one standard cell layout.
Claim 25
Dependent Claim
39 words
The storage means of claim 21 , wherein the standard cell layout includes hierarchical data and the pre-processed structures are stored on one of a first layer with cell data and a second layer dedicated to the pre-processed structures.
Claim 26
Dependent Claim
18 words
The storage means of claim 20 provided in a separate data file associated with a standard cell library.
Claim 27
Dependent Claim
10 words
The storage means of claim 20 provided within layout data.
Claim 28
Dependent Claim
42 words
The storage means of claim 24 , wherein the layout data includes hierarchical data and the pre-processed structures are stored on one of a first layer with a portion of the hierarchical data and a second layer dedicated to the pre-processed structures.
Claim 29
Independent Claim
75 words
A method of minimizing time for performing a processing operation on a chip layout, the method comprising: identifying a set of repeating structures within defined design units, each instance of the repeating structures having substantially the same proximity effect environment within a predetermined distance; pre-processing a representative repeating structure in the set of repeating structures during a non-critical time in chip design; and based on the pre-processing, performing the processing operation on the chip layout.
Claim 30
Independent Claim
75 words
A method of minimizing time for performing a processing operation on a chip layout, the method comprising: identifying a set of repeating structures within defined design units, each instance of the repeating structures having substantially the same proximity effect environment within a predetermined distance; pre-processing a representative repeating structure in the set of repeating structures during a non-critical time in chip design; and based on the pre-processing, performing the processing operation on the chip layout.
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2007-10-19 | 2008-04-19 | 2008-10-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2011-10-19 | 2012-04-19 | 2012-10-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2015-10-19 | 2016-04-19 | 2016-10-19 | $7700.00 | Window Closed / Lapsed |