Patent US1668438A successfully refreshed from Google Patents.
Patent US6718477B1 successfully refreshed from Google Patents.
US6718477B1
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Delay locked loop for an FPGA architecture
Assignee: Microsemi SoC Corp
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Filing: 2000-03-06
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Granted: 2004-04-06
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Expires: 2020-03-06
Abstract
Abstract A DLL provides a deskew mode for aligning a reference clock that passes through a clock distribution tree to a feedback by adding additional delay to the feedback clock to align the feedback clock with reference clock at one cycle later. A 0 ns clock-to-out mode is provided by adding additional delay to account for an input buffer into a feedback path. The feedback clock can be doubled by a clock doubler with 50% duty cycle adjustment disposed in the feedback path. Flexible timing is aligning the reference clock to the feedback clock is obtained with additional delay elements disposed in the feedback and reference clock paths.
Inventors
- 👤 William C. Plants
- 👤 Nikhil Mazumder
- 👤 Arunangshu Kundu
- 👤 James Joseph
- 👤 Wayne W. Wong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 23:17
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; G06F1/10
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
214 words
In an integrated circuit, a delay lock loop comprising: a reference delay line having a first input programmably coupled to one of an external clock and an internal clock and selectably coupled through an inverter programmably disposed in series with said reference delay line; a feedback delay line having an input programmably coupled to a feedback clock and selectably coupled through an inverter programmably disposed in series with said feedback delay line; a phase detector having an input programmably coupled to an output of said reference delay line and a second input coupled to an output of said feedback delay line, wherein said reference delay line and said feedback delay line are selectably coupled to said phase detector through a plurality of divide-by-two circuits; a control logic circuit having an input programmably coupled to an output of said phase detector; a programmable delay line having inputs programmably coupled to the control logic circuit to receive data, a clock input coupled to said reference clock and an output; a clock doubler having an input programmably coupled to said output of said delay line; and a clock tree having an input programmably coupled to an output of said clock doubler and an output forming the feedback clock coupled to said input of said feedback delay line.
Claim 2
Dependent Claim
214 words
In an integrated circuit, a delay lock loop comprising: a reference delay line having a first input programmably coupled to one of an external clock and an internal clock and selectably coupled through an inverter programmably disposed in series with said reference delay line; a feedback delay line having an input programmably coupled to a feedback clock and selectably coupled through an inverter programmably disposed in series with said feedback delay line; a phase detector having an input programmably coupled to an output of said reference delay line and a second input coupled to an output of said feedback delay line, wherein said reference delay line and said feedback delay line are selectably coupled to said phase detector through a plurality of divide-by-two circuits; a control logic circuit having an input programmably coupled to an output of said phase detector; a programmable delay line having inputs programmably coupled to the control logic circuit to receive data, a clock input coupled to said reference clock and an output; a clock doubler having an input programmably coupled to said output of said delay line; and a clock tree having an input programmably coupled to an output of said clock doubler and an output forming the feedback clock coupled to said input of said feedback delay line.
Claim 3
Dependent Claim
131 words
A delay lock loop as in claim 1 wherein said programmable delay line further comprises: a secondary delay line having a first input programmably coupled to said reference clock and a second input programmably coupled to said control logic circuit wherein said secondary delay line has a delay period controlled by a plurality of data bits received from said control logic circuit; a primary delay line having a first input programmably coupled to said an output of said secondary delay line and a second input programmably coupled to said control logic circuit wherein said primary delay line has a delay period controlled by a plurality of data bits received from said control logic circuit; and a pulse shaper having an input programmably coupled to an output of said primary delay line.
Claim 4
Dependent Claim
239 words
In an integrated circuit, a method of implementing a delay lock loop comprising: programmably coupling a reference delay line having an input to one of an external clock and an internal clock and selectably coupling said input of reference delay line through an inverter programmably disposed in series with said reference delay line; programmably coupling a feedback delay line having an input to a feedback clock and selectably coupling said input of said feedback delay line through an inverter programmably disposed in series with said feedback delay line; programmably coupling a phase detector having a first input to an output of said reference delay line and programmably coupling a second input of said phase detector to an output of said feedback delay line, wherein said reference delay line and said feedback delay line are selectably coupled to said phase detector through a plurality of divide-by-two circuits; programmably coupling a control circuit having an input to an output of said phase detector; programmably coupling a programmable delay line having data inputs to control logic circuit to receive data and programmably coupling a clock input of said programmable delay line to said reference clock; programmably coupling a clock doubler having an input to an output of said delay line; and programmably coupling a clock tree having an input to an output of said clock doubler and to an output forming the feedback clock to said input of said feedback delay line.
Claim 5
Dependent Claim
239 words
In an integrated circuit, a method of implementing a delay lock loop comprising: programmably coupling a reference delay line having an input to one of an external clock and an internal clock and selectably coupling said input of reference delay line through an inverter programmably disposed in series with said reference delay line; programmably coupling a feedback delay line having an input to a feedback clock and selectably coupling said input of said feedback delay line through an inverter programmably disposed in series with said feedback delay line; programmably coupling a phase detector having a first input to an output of said reference delay line and programmably coupling a second input of said phase detector to an output of said feedback delay line, wherein said reference delay line and said feedback delay line are selectably coupled to said phase detector through a plurality of divide-by-two circuits; programmably coupling a control circuit having an input to an output of said phase detector; programmably coupling a programmable delay line having data inputs to control logic circuit to receive data and programmably coupling a clock input of said programmable delay line to said reference clock; programmably coupling a clock doubler having an input to an output of said delay line; and programmably coupling a clock tree having an input to an output of said clock doubler and to an output forming the feedback clock to said input of said feedback delay line.
Claim 6
Dependent Claim
131 words
A delay lock loop as in claim 1 wherein said programmable delay line further comprises: a secondary delay line having a first input programmably coupled to said reference clock and a second input programmably coupled to said control logic circuit wherein said secondary delay line has a delay period controlled by a plurality of data bits received from said control logic circuit; a primary delay line having a first input programmably coupled to said an output of said secondary delay line and a second input programmably coupled to said control logic circuit wherein said primary delay line has a delay period controlled by a plurality of data bits received from said control logic circuit; and a pulse shaper having an input programmably coupled to an output of said primary delay line.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2007-04-06 | 2007-10-06 | 2008-04-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2011-04-06 | 2011-10-06 | 2012-04-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2015-04-06 | 2015-10-06 | 2016-04-06 | $7700.00 | Window Closed / Lapsed |