US6181174B1
Expired / Lapsed
US
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Semiconductor integrated circuit device
Assignee: Socionext Inc
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Filing: 1999-09-23
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Granted: 2001-01-30
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Expires: 2019-09-23
Abstract
Abstract A semiconductor integrated circuit device includes a DLL circuit. The DLL circuit includes a frequency divider which frequency-divides an input clock at a frequency dividing ratio which is varied depending on a frequency of the input clock and thus results in a dummy clock and a reference clock. A delay system includes a variable delay circuit which delays the dummy clock. A control circuit controls a delay amount of the variable delay circuit so that a phase of a delayed dummy clock from the delay system and the reference clock becomes zero.
Inventors
- 👤 Waichirou Fujieda
- 👤 Yasuharu Sato
- 👤 Nobutaka Taniguchi
- 👤 Hiroyoshi Tomita
- 👤 Yasurou Matsuzaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 20:48
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/0805; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406; G06; G06F; G06F1/00; G06F1/04; G06F1/08; G06F1/10; G11C11/4063; G11C11/407; G11C11/4076; G11C7/00; G11C7/10; G11C7/1015; G11C7/1039; G11C7/1045; G11C7/1072; G11C7/22; G11C7/222; H03K; H03K23/00; H03K23/58; H03K5/00; H03K5/13; H03K5/133; H03L7/081; H03L7/0812; H03L7/0814; H03L7/0816
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
93 words
A semiconductor integrated circuit device comprising: a delayed locked loop circuit including: a frequency divider which frequency-divides an input clock at a frequency dividing ratio which is varied depending on a frequency of the input clock and thus results in a dummy clock and a reference clock; a delay system including a variable delay circuit which delays the dummy clock; and a control circuit which controls a delay amount of the variable delay circuit so that a phase of a delayed dummy clock from the delay system and the reference clock becomes zero.
Claim 2
Dependent Claim
93 words
A semiconductor integrated circuit device comprising: a delayed locked loop circuit including: a frequency divider which frequency-divides an input clock at a frequency dividing ratio which is varied depending on a frequency of the input clock and thus results in a dummy clock and a reference clock; a delay system including a variable delay circuit which delays the dummy clock; and a control circuit which controls a delay amount of the variable delay circuit so that a phase of a delayed dummy clock from the delay system and the reference clock becomes zero.
Claim 3
Dependent Claim
31 words
The semiconductor integrated circuit device as claimed in claim 1 , wherein the frequency dividing ratio of the frequency divider is increased when the frequency of the input clock becomes higher.
Claim 4
Dependent Claim
36 words
The semiconductor integrated circuit device as claimed in claim 2 , wherein the frequency dividing ratio of the frequency divider is indicated by a frequency dividing ratio setting signal applied to the delayed locked loop circuit.
Claim 5
Dependent Claim
58 words
The semiconductor integrated circuit device as claimed in claim 1 , wherein the frequency divider comprises: a plurality of frequency dividing parts respectively having different frequency dividing ratios; and a selector circuit which selects one of the plurality of frequency dividing parts in accordance with a frequency dividing ratio setting signal applied to the delayed locked loop circuit.
Claim 6
Dependent Claim
29 words
The semiconductor integrated circuit device as claimed in claim 4 , wherein only said one of the plurality of frequency dividing parts selected by the selector circuit is enabled.
Claim 7
Dependent Claim
20 words
The semiconductor integrated circuit device as claimed in claim 1 , wherein said frequency divider is a variable frequency divider.
Claim 8
Dependent Claim
48 words
The semiconductor integrated circuit device as claimed in claim 1 , further comprising a frequency dividing ratio setting signal generating circuit which detects the frequency of the input clock and thus results in a frequency dividing ratio setting signal indicating the frequency dividing ratio of the frequency divider.
Claim 9
Dependent Claim
124 words
A semiconductor integrated circuit device comprising: a 1/2 frequency divider which frequency-divides an input clock at a frequency dividing ratio of 1/2; a selector circuit which selects one of the input clock and a frequency-divided clock from the 1/2 frequency divider in accordance with a frequency of the input clock; and a delayed locked loop circuit including: a frequency divider which frequency-divides a selected clock from the selector circuit and produces a dummy clock and a reference clock; a delay system including a variable delay circuit which delays the dummy clock; and a control circuit which controls a delay amount of the variable delay circuit so that a phase of a delayed dummy clock from the delay system and the reference clock becomes zero.
Claim 10
Dependent Claim
124 words
A semiconductor integrated circuit device comprising: a 1/2 frequency divider which frequency-divides an input clock at a frequency dividing ratio of 1/2; a selector circuit which selects one of the input clock and a frequency-divided clock from the 1/2 frequency divider in accordance with a frequency of the input clock; and a delayed locked loop circuit including: a frequency divider which frequency-divides a selected clock from the selector circuit and produces a dummy clock and a reference clock; a delay system including a variable delay circuit which delays the dummy clock; and a control circuit which controls a delay amount of the variable delay circuit so that a phase of a delayed dummy clock from the delay system and the reference clock becomes zero.
References Cited (Backward Citations)
US5929711A
Cited
US6066968A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-01-30 | 2004-07-31 | 2005-01-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-01-30 | 2008-07-31 | 2009-01-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-01-30 | 2012-07-31 | 2013-01-30 | $7700.00 | Window Closed / Lapsed |